ba72e28bf6adbfc4538ec03b3e2f3faebe92f898
2 # SPDX-License-Identifier: LGPL-2.1-or-later
3 # See Notices.txt for copyright information
5 from nmigen
import Signal
, Module
, Elaboratable
, Mux
, Cat
, Shape
, Repl
6 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
7 from nmigen
.cli
import rtlil
9 from ieee754
.part
.partsig
import SimdSignal
10 from ieee754
.part
.simd_scope
import SimdScope
12 from random
import randint
18 def create_ilang(dut
, traces
, test_name
):
19 vl
= rtlil
.convert(dut
, ports
=traces
)
20 with
open("%s.il" % test_name
, "w") as f
:
24 def create_simulator(module
, traces
, test_name
):
25 create_ilang(module
, traces
, test_name
)
26 return Simulator(module
)
30 class TestCatMod(Elaboratable
):
31 def __init__(self
, width
, elwid
, vec_el_counts
):
33 with
SimdScope(self
.m
, elwid
, vec_el_counts
) as s
:
34 # BE CAREFUL with the fixed_width parameter.
35 # it is NOT available in SimdScope.scalar mode
36 self
.a
= s
.Signal(fixed_width
=width
)
37 self
.b
= s
.Signal(fixed_width
=width
*2)
38 self
.o
= s
.Signal(fixed_width
=width
*3)
39 self
.cat_out
= self
.o
.sig
41 def elaborate(self
, platform
):
45 comb
+= self
.o
.eq(Cat(self
.a
, self
.b
))
50 class TestCat(unittest
.TestCase
):
53 elwid
= Signal(2) # elwid parameter
54 vec_el_counts
= {0b00: 1, 0b01: 2, 0b10: 4}
55 module
= TestCatMod(width
, elwid
, vec_el_counts
)
57 test_name
= "part_sig_cat_scope"
62 sim
= create_simulator(module
, traces
, test_name
)
64 # annoying recursive import issue
65 from ieee754
.part_cat
.cat
import get_runlengths
69 def test_catop(msg_prefix
):
70 # define lengths of a/b test input
72 # pairs of test values a, b
73 for a
, b
in [(0x0000, 0x00000000),
79 (0x0000, 0xFFFFFFFF)]:
81 # convert a and b to partitions
83 ajump
, bjump
= alen
// 4, blen
// 4
85 apart
.append((a
>> (ajump
*i
) & ((1<<ajump
)-1)))
86 bpart
.append((b
>> (bjump
*i
) & ((1<<bjump
)-1)))
88 print ("apart bpart", hex(a
), hex(b
),
89 list(map(hex, apart
)), list(map(hex, bpart
)))
91 yield module
.a
.lower().eq(a
)
92 yield module
.b
.lower().eq(b
)
96 # work out the runlengths for this mask.
97 # 0b011 returns [1,1,2] (for a mask of length 3)
99 runlengths
= get_runlengths(mval
, 3)
106 print ("runlength", i
,
108 "apart", hex(apart
[ai
]),
116 print ("runlength", i
,
118 "bpart", hex(bpart
[bi
]),
126 outval
= (yield module
.cat_out
)
127 msg
= f
"{msg_prefix}: cat " + \
128 f
"0x{mval:X} 0x{a:X} : 0x{b:X}" + \
129 f
" => 0x{y:X} != 0x{outval:X}"
130 self
.assertEqual(y
, outval
, msg
)
133 yield from test_catop("16-bit")
135 yield from test_catop("8-bit")
137 yield from test_catop("4-bit")
139 sim
.add_process(async_process
)
141 vcd_file
=open(test_name
+ ".vcd", "w"),
142 gtkw_file
=open(test_name
+ ".gtkw", "w"),
147 if __name__
== '__main__':