06046fa2a182d1cfbcb3b1f73b4c2f1c165f763d
[ieee754fpu.git] / src / ieee754 / part_cmp / experiments / gt_combiner.py
1 from nmigen import Signal, Module, Elaboratable, Mux
2 from ieee754.part_mul_add.partpoints import PartitionPoints
3
4 class Combiner(Elaboratable):
5 def __init__(self):
6 self.ina = Signal()
7 self.inb = Signal()
8 self.sel = Signal()
9 self.outa = Signal()
10 self.outb = Signal()
11 def elaborate(self, platform):
12 m = Module()
13 comb = m.d.comb
14
15 comb += self.outa.eq(Mux(self.sel, self.inb, self.ina))
16 comb += self.outb.eq(self.sel & self.ina)
17
18 return m
19
20 # This is similar to EQCombiner, except that for a greater than
21 # comparison, it needs to deal with both the greater than and equals
22 # signals from each partition. The signals are combined using a
23 # cascaded AND/OR to give the following effect:
24 # When a partition is open, the output is set if either the current
25 # partition's greater than flag is set, or the current partition's
26 # equal flag is set AND the previous partition's greater than output
27 # is true
28 class GTCombiner(Elaboratable):
29 def __init__(self, width):
30 self.width = width
31 self.mux_input = Signal(reset_less=True) # right hand side mux input
32 self.eqs = Signal(width, reset_less=True) # the flags for EQ
33 self.gts = Signal(width, reset_less=True) # the flags for GT
34 self.gates = Signal(width-1, reset_less=True)
35 self.outputs = Signal(width, reset_less=True)
36
37 def elaborate(self, platform):
38 m = Module()
39 comb = m.d.comb
40
41 previnput = self.gts[-1] | (self.eqs[-1] & self.mux_input)
42 for i in range(self.width-1, 0, -1): # counts down from width-1 to 1
43 m.submodules["mux%d" % i] = mux = Combiner()
44
45 comb += mux.ina.eq(previnput)
46 comb += mux.inb.eq(self.mux_input)
47 comb += mux.sel.eq(self.gates[i-1])
48 comb += self.outputs[i].eq(mux.outb)
49 previnput = self.gts[i-1] | (self.eqs[i-1] & mux.outa)
50
51 comb += self.outputs[0].eq(previnput)
52
53 return m
54
55 def ports(self):
56 return [self.eqs, self.gts, self.gates, self.outputs]