src/ieee754/part_shift/bitrev.py

   1 from nmigen import Signal, Module, Elaboratable, Cat, Mux
   2
   3 class GatedBitReverse(Elaboratable):
   4     def __init__(self, width):
   5         self.width = width
   6         self.data = Signal(width, reset_less=True)
   7         self.reverse_en = Signal(reset_less=True)
   8         self.output = Signal(width, reset_less=True)
   9     def elaborate(self, platform):
  10         m = Module()
  11         comb = m.d.comb
  12         width = self.width
  13
  14         for i in range(width):
  15             with m.If(self.reverse_en):
  16                 comb += self.output[i].eq(self.data[width-i-1])
  17             with m.Else():
  18                 comb += self.output[i].eq(self.data[i])
  19
  20         return m