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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "common/gen_device_info.h"
29 #include "main/mtypes.h"
30 #include "main/macros.h"
39 union gl_constant_value
;
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
107 * Program key structures.
109 * When drawing, we look for the currently bound shaders in the program
110 * cache. This is essentially a hash table lookup, and these are the keys.
112 * Sometimes OpenGL features specified as state need to be simulated via
113 * shader code, due to a mismatch between the API and the hardware. This
114 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
115 * in the program key so it's considered when searching for a program. If
116 * we haven't seen a particular combination before, we have to recompile a
117 * new specialized version.
119 * Shader compilation should not look up state in gl_context directly, but
120 * instead use the copy in the program key. This guarantees recompiles will
126 enum PACKED gen6_gather_sampler_wa
{
127 WA_SIGN
= 1, /* whether we need to sign extend */
128 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
129 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
133 * Sampler information needed by VS, WM, and GS program cache keys.
135 struct brw_sampler_prog_key_data
{
137 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
139 uint16_t swizzles
[MAX_SAMPLERS
];
141 uint32_t gl_clamp_mask
[3];
144 * For RG32F, gather4's channel select is broken.
146 uint32_t gather_channel_quirk_mask
;
149 * Whether this sampler uses the compressed multisample surface layout.
151 uint32_t compressed_multisample_layout_mask
;
154 * Whether this sampler is using 16x multisampling. If so fetching from
155 * this sampler will be handled with a different instruction, ld2dms_w
161 * For Sandybridge, which shader w/a we need for gather quirks.
163 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
166 * Texture units that have a YUV image bound.
168 uint32_t y_u_v_image_mask
;
169 uint32_t y_uv_image_mask
;
170 uint32_t yx_xuxv_image_mask
;
174 * The VF can't natively handle certain types of attributes, such as GL_FIXED
175 * or most 10_10_10_2 types. These flags enable various VS workarounds to
176 * "fix" attributes at the beginning of shaders.
178 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
179 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
180 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
181 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
182 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
184 /** The program key for Vertex Shaders. */
185 struct brw_vs_prog_key
{
186 unsigned program_string_id
;
189 * Per-attribute workaround flags
191 * For each attribute, a combination of BRW_ATTRIB_WA_*.
193 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
195 bool copy_edgeflag
:1;
197 bool clamp_vertex_color
:1;
200 * How many user clipping planes are being uploaded to the vertex shader as
203 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
206 unsigned nr_userclip_plane_consts
:4;
209 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
210 * are going to be replaced with point coordinates (as a consequence of a
211 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
212 * our SF thread requires exact matching between VS outputs and FS inputs,
213 * these texture coordinates will need to be unconditionally included in
214 * the VUE, even if they aren't written by the vertex shader.
216 uint8_t point_coord_replace
;
218 struct brw_sampler_prog_key_data tex
;
221 /** The program key for Tessellation Control Shaders. */
222 struct brw_tcs_prog_key
224 unsigned program_string_id
;
226 GLenum tes_primitive_mode
;
228 unsigned input_vertices
;
230 /** A bitfield of per-patch outputs written. */
231 uint32_t patch_outputs_written
;
233 /** A bitfield of per-vertex outputs written. */
234 uint64_t outputs_written
;
236 bool quads_workaround
;
238 struct brw_sampler_prog_key_data tex
;
241 /** The program key for Tessellation Evaluation Shaders. */
242 struct brw_tes_prog_key
244 unsigned program_string_id
;
246 /** A bitfield of per-patch inputs read. */
247 uint32_t patch_inputs_read
;
249 /** A bitfield of per-vertex inputs read. */
250 uint64_t inputs_read
;
252 struct brw_sampler_prog_key_data tex
;
255 /** The program key for Geometry Shaders. */
256 struct brw_gs_prog_key
258 unsigned program_string_id
;
260 struct brw_sampler_prog_key_data tex
;
263 /* A big lookup table is used to figure out which and how many
264 * additional regs will inserted before the main payload in the WM
265 * program execution. These mainly relate to depth and stencil
266 * processing and the early-depth-test optimization.
268 enum brw_wm_iz_bits
{
269 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
270 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
271 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
272 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
273 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
274 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
275 BRW_WM_IZ_BIT_MAX
= 0x40
278 enum brw_wm_aa_enable
{
284 /** The program key for Fragment/Pixel Shaders. */
285 struct brw_wm_prog_key
{
286 /* Some collection of BRW_WM_IZ_* */
290 unsigned nr_color_regions
:5;
291 bool replicate_alpha
:1;
292 bool clamp_fragment_color
:1;
293 bool persample_interp
:1;
294 bool multisample_fbo
:1;
295 bool frag_coord_adds_sample_pos
:1;
296 enum brw_wm_aa_enable line_aa
:2;
297 bool high_quality_derivatives
:1;
298 bool force_dual_color_blend
:1;
299 bool coherent_fb_fetch
:1;
301 uint16_t drawable_height
;
302 uint64_t input_slots_valid
;
303 unsigned program_string_id
;
304 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
305 float alpha_test_ref
;
307 struct brw_sampler_prog_key_data tex
;
310 struct brw_cs_prog_key
{
311 uint32_t program_string_id
;
312 struct brw_sampler_prog_key_data tex
;
316 * Image metadata structure as laid out in the shader parameter
317 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
318 * able to use them. That's okay because the padding and any unused
319 * entries [most of them except when we're doing untyped surface
320 * access] will be removed by the uniform packing pass.
322 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
323 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
324 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
325 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
326 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
327 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
328 #define BRW_IMAGE_PARAM_SIZE 24
330 struct brw_image_param
{
331 /** Surface binding table index. */
332 uint32_t surface_idx
;
334 /** Offset applied to the X and Y surface coordinates. */
337 /** Surface X, Y and Z dimensions. */
340 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
341 * pixels, vertical slice stride in pixels.
345 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
349 * Right shift to apply for bit 6 address swizzling. Two different
350 * swizzles can be specified and will be applied one after the other. The
351 * resulting address will be:
353 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
354 * (addr >> swizzling[1])))
356 * Use \c 0xff if any of the swizzles is not required.
358 uint32_t swizzling
[2];
361 /** Max number of render targets in a shader */
362 #define BRW_MAX_DRAW_BUFFERS 8
365 * Max number of binding table entries used for stream output.
367 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
368 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
370 * On Gen6, the size of transform feedback data is limited not by the number
371 * of components but by the number of binding table entries we set aside. We
372 * use one binding table entry for a float, one entry for a vector, and one
373 * entry per matrix column. Since the only way we can communicate our
374 * transform feedback capabilities to the client is via
375 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
376 * worst case, in which all the varyings are floats, so we use up one binding
377 * table entry per component. Therefore we need to set aside at least 64
378 * binding table entries for use by transform feedback.
380 * Note: since we don't currently pack varyings, it is currently impossible
381 * for the client to actually use up all of these binding table entries--if
382 * all of their varyings were floats, they would run out of varying slots and
383 * fail to link. But that's a bug, so it seems prudent to go ahead and
384 * allocate the number of binding table entries we will need once the bug is
387 #define BRW_MAX_SOL_BINDINGS 64
390 * Binding table index for the first gen6 SOL binding.
392 #define BRW_GEN6_SOL_BINDING_START 0
395 * Stride in bytes between shader_time entries.
397 * We separate entries by a cacheline to reduce traffic between EUs writing to
400 #define BRW_SHADER_TIME_STRIDE 64
402 struct brw_stage_prog_data
{
404 /** size of our binding table. */
408 * surface indices for the various groups of surfaces
410 uint32_t pull_constants_start
;
411 uint32_t texture_start
;
412 uint32_t gather_texture_start
;
416 uint32_t image_start
;
417 uint32_t shader_time_start
;
418 uint32_t plane_start
[3];
422 GLuint nr_params
; /**< number of float params/constants */
423 GLuint nr_pull_params
;
424 unsigned nr_image_params
;
426 unsigned curb_read_length
;
427 unsigned total_scratch
;
428 unsigned total_shared
;
431 * Register where the thread expects to find input data from the URB
432 * (typically uniforms, followed by vertex or fragment attributes).
434 unsigned dispatch_grf_start_reg
;
436 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
438 /* Pointers to tracked values (only valid once
439 * _mesa_load_state_parameters has been called at runtime).
441 const union gl_constant_value
**param
;
442 const union gl_constant_value
**pull_param
;
444 /** Image metadata passed to the shader as uniforms. */
445 struct brw_image_param
*image_param
;
449 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
452 /* A binding table index is 8 bits and the top 3 values are reserved for
453 * special things (stateless and SLM).
455 assert(surf_index
<= 252);
457 prog_data
->binding_table
.size_bytes
=
458 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
461 enum brw_barycentric_mode
{
462 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
463 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
464 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
465 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
466 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
467 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
468 BRW_BARYCENTRIC_MODE_COUNT
= 6
470 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
471 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
472 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
473 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
475 enum brw_pixel_shader_computed_depth_mode
{
476 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
477 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
478 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
479 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
482 /* Data about a particular attempt to compile a program. Note that
483 * there can be many of these, each in a different GL state
484 * corresponding to a different brw_wm_prog_key struct, with different
487 struct brw_wm_prog_data
{
488 struct brw_stage_prog_data base
;
490 GLuint num_varying_inputs
;
492 uint8_t reg_blocks_0
;
493 uint8_t reg_blocks_2
;
495 uint8_t dispatch_grf_start_reg_2
;
496 uint32_t prog_offset_2
;
500 * surface indices the WM-specific surfaces
502 uint32_t render_target_start
;
503 uint32_t render_target_read_start
;
507 uint8_t computed_depth_mode
;
508 bool computed_stencil
;
510 bool early_fragment_tests
;
511 bool post_depth_coverage
;
516 bool persample_dispatch
;
517 bool uses_pos_offset
;
522 bool uses_sample_mask
;
523 bool has_side_effects
;
526 bool contains_flat_varying
;
527 bool contains_noperspective_varying
;
530 * Mask of which interpolation modes are required by the fragment shader.
531 * Used in hardware setup on gen6+.
533 uint32_t barycentric_interp_modes
;
536 * Mask of which FS inputs are marked flat by the shader source. This is
537 * needed for setting up 3DSTATE_SF/SBE.
539 uint32_t flat_inputs
;
541 /* Mapping of VUE slots to interpolation modes.
542 * Used by the Gen4-5 clip/sf/wm stages.
544 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
547 * Map from gl_varying_slot to the position within the FS setup data
548 * payload where the varying's attribute vertex deltas should be delivered.
549 * For varying slots that are not used by the FS, the value is -1.
551 int urb_setup
[VARYING_SLOT_MAX
];
554 struct brw_push_const_block
{
555 unsigned dwords
; /* Dword count, not reg aligned */
557 unsigned size
; /* Bytes, register aligned */
560 struct brw_cs_prog_data
{
561 struct brw_stage_prog_data base
;
563 GLuint dispatch_grf_start_reg_16
;
564 unsigned local_size
[3];
568 bool uses_num_work_groups
;
569 int thread_local_id_index
;
572 struct brw_push_const_block cross_thread
;
573 struct brw_push_const_block per_thread
;
574 struct brw_push_const_block total
;
579 * surface indices the CS-specific surfaces
581 uint32_t work_groups_start
;
587 * Enum representing the i965-specific vertex results that don't correspond
588 * exactly to any element of gl_varying_slot. The values of this enum are
589 * assigned such that they don't conflict with gl_varying_slot.
593 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
594 BRW_VARYING_SLOT_PAD
,
596 * Technically this is not a varying but just a placeholder that
597 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
598 * builtin variable to be compiled correctly. see compile_sf_prog() for
601 BRW_VARYING_SLOT_PNTC
,
602 BRW_VARYING_SLOT_COUNT
606 * We always program SF to start reading at an offset of 1 (2 varying slots)
607 * from the start of the vertex URB entry. This causes it to skip:
608 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
609 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
611 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
614 * Bitmask indicating which fragment shader inputs represent varyings (and
615 * hence have to be delivered to the fragment shader by the SF/SBE stage).
617 #define BRW_FS_VARYING_INPUT_MASK \
618 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
619 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
622 * Data structure recording the relationship between the gl_varying_slot enum
623 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
624 * single octaword within the VUE (128 bits).
626 * Note that each BRW register contains 256 bits (2 octawords), so when
627 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
628 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
629 * in a vertex shader), each register corresponds to a single VUE slot, since
630 * it contains data for two separate vertices.
634 * Bitfield representing all varying slots that are (a) stored in this VUE
635 * map, and (b) actually written by the shader. Does not include any of
636 * the additional varying slots defined in brw_varying_slot.
638 uint64_t slots_valid
;
641 * Is this VUE map for a separate shader pipeline?
643 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
644 * without the linker having a chance to dead code eliminate unused varyings.
646 * This means that we have to use a fixed slot layout, based on the output's
647 * location field, rather than assigning slots in a compact contiguous block.
652 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
653 * not stored in a slot (because they are not written, or because
654 * additional processing is applied before storing them in the VUE), the
657 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
660 * Map from VUE slot to gl_varying_slot value. For slots that do not
661 * directly correspond to a gl_varying_slot, the value comes from
664 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
666 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
669 * Total number of VUE slots in use
674 * Number of per-patch VUE slots. Only valid for tessellation control
675 * shader outputs and tessellation evaluation shader inputs.
677 int num_per_patch_slots
;
680 * Number of per-vertex VUE slots. Only valid for tessellation control
681 * shader outputs and tessellation evaluation shader inputs.
683 int num_per_vertex_slots
;
686 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
689 * Convert a VUE slot number into a byte offset within the VUE.
691 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
697 * Convert a vertex output (brw_varying_slot) into a byte offset within the
701 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
703 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
706 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
707 struct brw_vue_map
*vue_map
,
708 uint64_t slots_valid
,
709 bool separate_shader
);
711 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
712 uint64_t slots_valid
,
715 /* brw_interpolation_map.c */
716 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
717 struct nir_shader
*nir
,
718 struct brw_wm_prog_data
*prog_data
,
719 const struct gen_device_info
*devinfo
);
721 enum shader_dispatch_mode
{
722 DISPATCH_MODE_4X1_SINGLE
= 0,
723 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
724 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
725 DISPATCH_MODE_SIMD8
= 3,
729 * @defgroup Tessellator parameter enumerations.
731 * These correspond to the hardware values in 3DSTATE_TE, and are provided
732 * as part of the tessellation evaluation shader.
736 enum brw_tess_partitioning
{
737 BRW_TESS_PARTITIONING_INTEGER
= 0,
738 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
739 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
742 enum brw_tess_output_topology
{
743 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
744 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
745 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
746 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
749 enum brw_tess_domain
{
750 BRW_TESS_DOMAIN_QUAD
= 0,
751 BRW_TESS_DOMAIN_TRI
= 1,
752 BRW_TESS_DOMAIN_ISOLINE
= 2,
756 struct brw_vue_prog_data
{
757 struct brw_stage_prog_data base
;
758 struct brw_vue_map vue_map
;
760 /** Should the hardware deliver input VUE handles for URB pull loads? */
761 bool include_vue_handles
;
763 GLuint urb_read_length
;
766 uint32_t clip_distance_mask
;
767 uint32_t cull_distance_mask
;
769 /* Used for calculating urb partitions. In the VS, this is the size of the
770 * URB entry used for both input and output to the thread. In the GS, this
771 * is the size of the URB entry used for output.
773 GLuint urb_entry_size
;
775 enum shader_dispatch_mode dispatch_mode
;
778 struct brw_vs_prog_data
{
779 struct brw_vue_prog_data base
;
781 GLbitfield64 inputs_read
;
782 GLbitfield64 double_inputs_read
;
784 unsigned nr_attributes
;
785 unsigned nr_attribute_slots
;
788 bool uses_instanceid
;
789 bool uses_basevertex
;
790 bool uses_baseinstance
;
794 struct brw_tcs_prog_data
796 struct brw_vue_prog_data base
;
798 /** Number vertices in output patch */
803 struct brw_tes_prog_data
805 struct brw_vue_prog_data base
;
807 enum brw_tess_partitioning partitioning
;
808 enum brw_tess_output_topology output_topology
;
809 enum brw_tess_domain domain
;
812 struct brw_gs_prog_data
814 struct brw_vue_prog_data base
;
816 unsigned vertices_in
;
819 * Size of an output vertex, measured in HWORDS (32 bytes).
821 unsigned output_vertex_size_hwords
;
823 unsigned output_topology
;
826 * Size of the control data (cut bits or StreamID bits), in hwords (32
827 * bytes). 0 if there is no control data.
829 unsigned control_data_header_size_hwords
;
832 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
833 * if the control data is StreamID bits, or
834 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
835 * Ignored if control_data_header_size is 0.
837 unsigned control_data_format
;
839 bool include_primitive_id
;
842 * The number of vertices emitted, if constant - otherwise -1.
844 int static_vertex_count
;
849 * Gen6: Provoking vertex convention for odd-numbered triangles
855 * Gen6: Number of varyings that are output to transform feedback.
857 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
860 * Gen6: Map from the index of a transform feedback binding table entry to the
861 * gl_varying_slot that should be streamed out through that binding table
864 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
867 * Gen6: Map from the index of a transform feedback binding table entry to the
868 * swizzles that should be used when streaming out data through that
869 * binding table entry.
871 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
874 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
875 static inline struct brw_##stage##_prog_data * \
876 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
878 return (struct brw_##stage##_prog_data *) prog_data; \
880 DEFINE_PROG_DATA_DOWNCAST(vue
)
881 DEFINE_PROG_DATA_DOWNCAST(vs
)
882 DEFINE_PROG_DATA_DOWNCAST(tcs
)
883 DEFINE_PROG_DATA_DOWNCAST(tes
)
884 DEFINE_PROG_DATA_DOWNCAST(gs
)
885 DEFINE_PROG_DATA_DOWNCAST(wm
)
886 DEFINE_PROG_DATA_DOWNCAST(cs
)
887 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
888 DEFINE_PROG_DATA_DOWNCAST(clip
)
889 DEFINE_PROG_DATA_DOWNCAST(sf
)
890 #undef DEFINE_PROG_DATA_DOWNCAST
894 struct brw_compiler
*
895 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
898 * Compile a vertex shader.
900 * Returns the final assembly and the program's size.
903 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
905 const struct brw_vs_prog_key
*key
,
906 struct brw_vs_prog_data
*prog_data
,
907 const struct nir_shader
*shader
,
908 gl_clip_plane
*clip_planes
,
909 bool use_legacy_snorm_formula
,
910 int shader_time_index
,
911 unsigned *final_assembly_size
,
915 * Compile a tessellation control shader.
917 * Returns the final assembly and the program's size.
920 brw_compile_tcs(const struct brw_compiler
*compiler
,
923 const struct brw_tcs_prog_key
*key
,
924 struct brw_tcs_prog_data
*prog_data
,
925 const struct nir_shader
*nir
,
926 int shader_time_index
,
927 unsigned *final_assembly_size
,
931 * Compile a tessellation evaluation shader.
933 * Returns the final assembly and the program's size.
936 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
938 const struct brw_tes_prog_key
*key
,
939 const struct brw_vue_map
*input_vue_map
,
940 struct brw_tes_prog_data
*prog_data
,
941 const struct nir_shader
*shader
,
942 struct gl_program
*prog
,
943 int shader_time_index
,
944 unsigned *final_assembly_size
,
948 * Compile a vertex shader.
950 * Returns the final assembly and the program's size.
953 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
955 const struct brw_gs_prog_key
*key
,
956 struct brw_gs_prog_data
*prog_data
,
957 const struct nir_shader
*shader
,
958 struct gl_program
*prog
,
959 int shader_time_index
,
960 unsigned *final_assembly_size
,
964 * Compile a fragment shader.
966 * Returns the final assembly and the program's size.
969 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
971 const struct brw_wm_prog_key
*key
,
972 struct brw_wm_prog_data
*prog_data
,
973 const struct nir_shader
*shader
,
974 struct gl_program
*prog
,
975 int shader_time_index8
,
976 int shader_time_index16
,
978 bool use_rep_send
, struct brw_vue_map
*vue_map
,
979 unsigned *final_assembly_size
,
983 * Compile a compute shader.
985 * Returns the final assembly and the program's size.
988 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
990 const struct brw_cs_prog_key
*key
,
991 struct brw_cs_prog_data
*prog_data
,
992 const struct nir_shader
*shader
,
993 int shader_time_index
,
994 unsigned *final_assembly_size
,
997 static inline uint32_t
998 encode_slm_size(unsigned gen
, uint32_t bytes
)
1000 uint32_t slm_size
= 0;
1002 /* Shared Local Memory is specified as powers of two, and encoded in
1003 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1005 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1006 * -------------------------------------------------------------------
1007 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1008 * -------------------------------------------------------------------
1009 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1011 assert(bytes
<= 64 * 1024);
1014 /* Shared Local Memory Size is specified as powers of two. */
1015 slm_size
= util_next_power_of_two(bytes
);
1018 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1019 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1021 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1022 slm_size
= MAX2(slm_size
, 4096) / 4096;
1030 * Return true if the given shader stage is dispatched contiguously by the
1031 * relevant fixed function starting from channel 0 of the SIMD thread, which
1032 * implies that the dispatch mask of a thread can be assumed to have the form
1033 * '2^n - 1' for some n.
1036 brw_stage_has_packed_dispatch(const struct gen_device_info
*devinfo
,
1037 gl_shader_stage stage
,
1038 const struct brw_stage_prog_data
*prog_data
)
1040 /* The code below makes assumptions about the hardware's thread dispatch
1041 * behavior that could be proven wrong in future generations -- Make sure
1042 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1043 * the NIR front-end before changing this assertion.
1045 assert(devinfo
->gen
<= 9);
1048 case MESA_SHADER_FRAGMENT
: {
1049 /* The PSD discards subspans coming in with no lit samples, which in the
1050 * per-pixel shading case implies that each subspan will either be fully
1051 * lit (due to the VMask being used to allow derivative computations),
1052 * or not dispatched at all. In per-sample dispatch mode individual
1053 * samples from the same subspan have a fixed relative location within
1054 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1055 * general and we should return false.
1057 const struct brw_wm_prog_data
*wm_prog_data
=
1058 (const struct brw_wm_prog_data
*)prog_data
;
1059 return !wm_prog_data
->persample_dispatch
;
1061 case MESA_SHADER_COMPUTE
:
1062 /* Compute shaders will be spawned with either a fully enabled dispatch
1063 * mask or with whatever bottom/right execution mask was given to the
1064 * GPGPU walker command to be used along the workgroup edges -- In both
1065 * cases the dispatch mask is required to be tightly packed for our
1066 * invocation index calculations to work.
1070 /* Most remaining fixed functions are limited to use a packed dispatch
1071 * mask due to the hardware representation of the dispatch mask as a
1072 * single counter representing the number of enabled channels.
1082 #endif /* BRW_COMPILER_H */