1 // See LICENSE for license details.
2 package sifive.blocks.devices.uart
7 import uncore.tilelink2._
10 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
12 case class UARTParams(
16 divisorBits: Int = 16,
22 trait HasUARTParameters {
24 def uartDataBits = c.dataBits
25 def uartStopBits = c.stopBits
26 def uartDivisorBits = c.divisorBits
28 def uartOversample = c.oversample
29 def uartOversampleFactor = 1 << uartOversample
30 def uartNSamples = c.nSamples
32 def uartNTxEntries = c.nTxEntries
33 def uartNRxEntries = c.nRxEntries
35 require(uartDivisorBits > uartOversample)
36 require(uartOversampleFactor > uartNSamples)
39 abstract class UARTModule(val c: UARTParams)(implicit val p: Parameters)
40 extends Module with HasUARTParameters
42 class UARTPortIO extends Bundle {
43 val txd = Bool(OUTPUT)
47 trait HasUARTTopBundleContents extends Bundle {
48 val port = new UARTPortIO
51 class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
54 val in = Decoupled(Bits(width = uartDataBits)).flip
55 val out = Bits(OUTPUT, 1)
56 val div = UInt(INPUT, uartDivisorBits)
57 val nstop = UInt(INPUT, log2Up(uartStopBits))
60 val prescaler = Reg(init = UInt(0, uartDivisorBits))
61 val pulse = (prescaler === UInt(0))
63 private val n = uartDataBits + 1
64 val counter = Reg(init = UInt(0, log2Floor(n + uartStopBits) + 1))
65 val shifter = Reg(Bits(width = n))
66 val out = Reg(init = Bits(1, 1))
69 val busy = (counter =/= UInt(0))
70 io.in.ready := io.en && !busy
72 printf("%c", io.in.bits)
73 shifter := Cat(io.in.bits, Bits(0, 1))
74 counter := Mux1H((0 until uartStopBits).map(i =>
75 (io.nstop === UInt(i)) -> UInt(n + i + 1)))
78 prescaler := Mux(pulse, io.div, prescaler - UInt(1))
80 when (pulse && busy) {
81 counter := counter - UInt(1)
82 shifter := Cat(Bits(1, 1), shifter >> 1)
87 class UARTRx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
90 val in = Bits(INPUT, 1)
91 val out = Valid(Bits(width = uartDataBits))
92 val div = UInt(INPUT, uartDivisorBits)
95 val debounce = Reg(init = UInt(0, 2))
96 val debounce_max = (debounce === UInt(3))
97 val debounce_min = (debounce === UInt(0))
99 val prescaler = Reg(init = UInt(0, uartDivisorBits - uartOversample))
100 val start = Wire(init = Bool(false))
101 val busy = Wire(init = Bool(false))
102 val pulse = (prescaler === UInt(0)) && busy
105 prescaler := prescaler - UInt(1)
107 when (start || pulse) {
108 prescaler := io.div >> uartOversample
111 val sample = Reg(Bits(width = uartNSamples))
112 val voter = Majority(sample.toBools.toSet)
114 sample := Cat(sample, io.in)
117 private val delay0 = (uartOversampleFactor + uartNSamples) >> 1
118 private val delay1 = uartOversampleFactor
120 val timer = Reg(UInt(width = uartOversample + 1))
121 val counter = Reg(UInt(width = log2Floor(uartDataBits) + 1))
122 val shifter = Reg(Bits(width = uartDataBits))
123 val expire = (timer === UInt(0)) && pulse
125 val sched = Wire(init = Bool(false))
127 timer := timer - UInt(1)
130 timer := UInt(delay1-1)
133 val valid = Reg(init = Bool(false))
135 io.out.valid := valid
136 io.out.bits := shifter
138 val (s_idle :: s_start :: s_data :: Nil) = Enum(UInt(), 3)
139 val state = Reg(init = s_idle)
143 when (!(!io.in) && !debounce_min) {
144 debounce := debounce - UInt(1)
147 debounce := debounce + UInt(1)
148 when (debounce_max) {
151 timer := UInt(delay0-1)
164 counter := UInt(uartDataBits)
172 counter := counter - UInt(1)
173 when (counter === UInt(0)) {
177 shifter := Cat(voter, shifter >> 1)
189 class UARTInterrupts extends Bundle {
194 trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
195 val io: HasUARTTopBundleContents
196 implicit val p: Parameters
197 def params: UARTParams
200 val txm = Module(new UARTTx(params))
201 val txq = Module(new Queue(txm.io.in.bits, uartNTxEntries))
203 val rxm = Module(new UARTRx(params))
204 val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
206 val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200
207 val div = Reg(init = UInt(divinit, uartDivisorBits))
209 private val stopCountBits = log2Up(uartStopBits)
210 private val txCountBits = log2Floor(uartNTxEntries) + 1
211 private val rxCountBits = log2Floor(uartNRxEntries) + 1
213 val txen = Reg(init = Bool(false))
214 val rxen = Reg(init = Bool(false))
215 val txwm = Reg(init = UInt(0, txCountBits))
216 val rxwm = Reg(init = UInt(0, rxCountBits))
217 val nstop = Reg(init = UInt(0, stopCountBits))
220 txm.io.in <> txq.io.deq
222 txm.io.nstop := nstop
223 io.port.txd := txm.io.out
226 rxm.io.in := io.port.rxd
227 rxq.io.enq <> rxm.io.out
230 val ie = Reg(init = new UARTInterrupts().fromBits(Bits(0)))
231 val ip = Wire(new UARTInterrupts)
233 ip.txwm := (txq.io.count < txwm)
234 ip.rxwm := (rxq.io.count > rxwm)
235 interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
238 UARTCtrlRegs.txfifo -> NonBlockingEnqueue(txq.io.enq),
239 UARTCtrlRegs.rxfifo -> NonBlockingDequeue(rxq.io.deq),
241 UARTCtrlRegs.txctrl -> Seq(
243 RegField(stopCountBits, nstop)),
244 UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen)),
245 UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm)),
246 UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm)),
248 UARTCtrlRegs.ie -> Seq(
249 RegField(1, ie.txwm),
250 RegField(1, ie.rxwm)),
252 UARTCtrlRegs.ip -> Seq(
253 RegField.r(1, ip.txwm),
254 RegField.r(1, ip.rxwm)),
256 UARTCtrlRegs.div -> Seq(
257 RegField(uartDivisorBits, div))
261 // Magic TL2 Incantation to create a TL2 UART
262 class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
263 extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
264 new TLRegBundle(c, _) with HasUARTTopBundleContents)(
265 new TLRegModule(c, _, _) with HasUARTTopModuleContents)