1 // See LICENSE for license details.
2 package sifive.blocks.devices.xilinxvc707mig
5 import freechips.rocketchip.coreplex.HasMemoryBus
6 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
8 trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
9 val module: HasMemoryXilinxVC707MIGModuleImp
11 val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
13 require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
14 xilinxvc707mig.node := memBuses.head.toDRAMController
17 trait HasMemoryXilinxVC707MIGBundle {
18 val xilinxvc707mig: XilinxVC707MIGIO
19 def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
20 pads <> xilinxvc707mig
24 trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
25 with HasMemoryXilinxVC707MIGBundle {
26 val outer: HasMemoryXilinxVC707MIG
27 val xilinxvc707mig = IO(new XilinxVC707MIGIO)
29 xilinxvc707mig <> outer.xilinxvc707mig.module.io.port