6 period
= 20 # clk frequency = 50 MHz
10 def mux4(clk
, in_a
, in_b
, in_c
, in_d
,
12 sel_r
= Signal(intbv(0)[2:0])
13 sel25
= Signal(intbv(0)[4:0])
15 #@always(clk.posedge, reset_n.negedge)
20 # out.next = count_next
23 def logic_selection():
26 @always(clk
.posedge
, sel_r
)
29 sel25
.next
= intbv(0)[2:0]
31 if selector
== intbv(0)[2:0]:
32 sel25
.next
= intbv(1)[4:0]
33 if selector
== intbv(1)[2:0]:
34 sel25
.next
= intbv(2)[4:0]
35 if selector
== intbv(2)[2:0]:
36 sel25
.next
= intbv(4)[4:0]
37 if selector
== intbv(3)[2:0]:
38 sel25
.next
= intbv(8)[4:0]
40 #@always(clk.posedge, clk.negedge)
41 @always(sel25
, in_a
, in_b
, in_c
, in_d
)
43 out
.next
= bool(in_a
if sel25
[0] else False) | \
44 bool(in_b
if sel25
[1] else False) | \
45 bool(in_c
if sel25
[2] else False) | \
46 bool(in_d
if sel25
[3] else False)
48 return instances() # return all instances
56 in_a
= Signal(intbv(0)[1:0])
57 in_b
= Signal(intbv(0)[1:0])
58 in_c
= Signal(intbv(0)[1:0])
59 in_d
= Signal(intbv(0)[1:0])
60 selector
= Signal(intbv(0)[2:0])
63 mux_inst
= mux4(clk
, in_a
, in_b
, in_c
, in_d
, selector
, out
)
81 selector
.next
= selector
+ 1
82 yield delay(period
// 2)
84 # print simulation data on screen and file
85 file_data
= open("mux.csv", 'w') # file for saving data
86 # # print header on screen
87 s
= "{0},{1},{2},{3},{4},{5}".format("in_a", "in_b", "in_c", "in_d",
90 # # print header to file
92 # print data on each clock
97 # print.format is not supported in MyHDL 1.0
98 print ("%s,%s,%s,%s,%s,%s" %
104 # print.format is not supported in MyHDL 1.0
105 #file_data.write(s + "\n")
112 clk
= Signal(bool(0))
113 in_a
= Signal(intbv(0)[1:0])
114 in_b
= Signal(intbv(0)[1:0])
115 in_c
= Signal(intbv(0)[1:0])
116 in_d
= Signal(intbv(0)[1:0])
117 selector
= Signal(intbv(0)[2:0])
118 out
= Signal(bool(0))
120 mux_v
= mux4(clk
, in_a
, in_b
, in_c
, in_d
, selector
, out
)
121 mux_v
.convert(hdl
="Verilog", initial_values
=True)
125 tb
.convert(hdl
="Verilog", initial_values
=True)
126 # keep following lines below the 'tb.convert' line
127 # otherwise error will be reported
128 tb
.config_sim(trace
=True)
129 tb
.run_sim(66 * period
) # run for 15 clock cycle
132 if __name__
== '__main__':