4 from myhdl
._block
import _Block
9 from functools
import wraps
, partial
12 period
= 20 # clk frequency = 50 MHz
16 def __init__(self
, typ
, name
):
19 if typ
== 'in' or typ
== 'inout':
20 self
.inp
= Signal(bool(0))
21 if typ
== 'out' or typ
== 'inout':
22 self
.out
= Signal(bool(0))
24 self
.dirn
= Signal(bool(0))
28 def __init__(self
, bwidth
=2):
29 self
.sel
= Signal(intbv(0)[bwidth
:0])
33 print('attr =', obj
.attr
)
37 def cvt(self
, *args
, **kwargs
):
38 print('args', self
, args
, kwargs
)
39 return block(test2
)(*self
._args
).convert(*args
, **kwargs
)
55 def create_test(fncls
, npins
=2, nfns
=4):
57 from myhdl import block
59 def test(testfn, clk, fncls, num_pins, num_fns, {0}):
61 return testfn(clk, fncls, num_pins, num_fns, args)
65 for pnum
in range(npins
):
66 args
.append("sel%d" % pnum
)
67 args
.append("pin%d" % pnum
)
68 # for pnum in range(nfns):
69 # args.append("fn%d" % pnum)
74 with
open("testmod.py", "w") as f
:
76 x
= "from testmod import test"
77 code
= compile(x
, '<string>', 'exec')
89 return func(args
[0], args
[1], args
[2], args
[3])
95 self
.attrs
= ['uart', 'i2c', 'spi', 'gpio']
97 def setfn(self
, idx
, fn
):
98 return setattr(self
, self
.attrs
[idx
], fn
)
100 def getfn(self
, idx
):
101 return getattr(self
, self
.attrs
[idx
])
105 def muxer(clk
, p
, ifaces
, args
):
109 for i
in range(len(p
.muxed_cells
)):
110 pins
.append(args
.pop(0))
111 muxes
.append(args
.pop(0))
112 kl
= sorted(ifaces
.keys())
113 for i
in range(len(p
.myhdlifaces
)):
114 fns
.append(args
.pop(0))
120 x
= getattr(fns
[i
], fns
[i
].pnames
[0])
122 inputs
.append(getattr(fns
[i
], fns
[i
].pnames
[0]).out
)
123 inputs
.append(getattr(fns
[i
], fns
[i
].pnames
[0]).out
)
125 print "inputs", inputs
127 for i
in range(len(muxes
)):
132 inst
= mux4(clk
, inputs
, mux
.sel
, pin
.out
)
139 def test2(clk
, fncls
, num_pins
, num_fns
, args
):
142 for i
in range(num_pins
):
143 muxes
.append(args
.pop(0))
144 pins
.append(args
.pop(0))
149 inputs
.append(fncls
.uart
.out
)
150 inputs
.append(fncls
.i2c
.out
)
151 inputs
.append(fncls
.spi
.out
)
152 inputs
.append(fncls
.gpio
.out
)
154 # inputs.append(fncls.getfn(i).out)
156 for i
in range(len(muxes
)):
159 inst
= mux4(clk
, inputs
, mux
.sel
, pin
.out
)
181 muxvals
.append(m
.sel
)
183 pin
= IO("inout", "name%d" % i
)
188 dirs
.append(pin
.dirn
)
190 clk
= Signal(bool(0))
192 mux_inst
= test(test2
, clk
, fncls
, 2, 4, *args
)
198 yield delay(period
// 2)
203 # print.format is not supported in MyHDL 1.0
204 for i
in range(len(muxes
)):
207 print ("%d: %s %s" % (i
, sel
, out
))
232 muxvals
.append(m
.sel
)
234 pin
= IO("inout", "name%d" % i
)
239 dirs
.append(pin
.dirn
)
240 clk
= Signal(bool(0))
242 mux_inst
= test(test2
, clk
, fncls
, 2, 4, *args
)
243 mux_inst
.convert(hdl
="Verilog", initial_values
=True, testbench
=False)
244 #mux_inst = Test(clk, muxes, pins, fns)
245 #toVerilog(mux_inst, clk, muxes, pins, fns)
247 #b = _Block(mux_inst, deco, "test", "test.py", 1, clk, muxes, pins, fns)
248 #b.convert(hdl="Verilog", name="test", initial_values=True)
249 #mux_inst.convert(hdl="Verilog", initial_values=True)
250 #block(mux_inst).convert(hdl="Verilog", initial_values=True)
254 tb
.convert(hdl
="Verilog", initial_values
=True, testbench
=True)
255 # keep following lines below the 'tb.convert' line
256 # otherwise error will be reported
257 tb
.config_sim(trace
=True)
258 tb
.run_sim(66 * period
) # run for 15 clock cycle
261 def muxgen(fn
, p
, ifaces
):
263 for i
in range(len(p
.muxed_cells
)):
264 args
.append(p
.muxers
[i
])
265 args
.append(p
.muxsel
[i
])
266 for i
in p
.myhdlifaces
:
268 clk
= Signal(bool(0))
270 mux_inst
= fn(muxer
, clk
, p
, ifaces
, *args
)
271 mux_inst
.convert(hdl
="Verilog", initial_values
=True, testbench
=False)
274 if __name__
== '__main__':
277 for i
in range(num_fns
):
278 fn
= IO("inout", fncls
.attrs
[i
])
280 test
= create_test(fncls
)