2 This work is funded through NLnet under Grant 2019-02-012
8 from nmigen
.compat
.sim
import run_simulation
9 from nmigen
.cli
import verilog
, rtlil
10 from nmigen
import Record
, Signal
, Module
, Const
, Elaboratable
, Mux
14 module jk(q,q1,j,k,c);
18 initial begin q=1'b0; q1=1'b1; end
22 {1'b0,1'b0}:begin q=q; q1=q1; end
23 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
24 {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
25 {1'b1,1'b1}: begin q=~q; q1=~q1; end
32 def latchregister(m
, incoming
, outgoing
, settrue
, name
=None):
35 based on a conditon, "settrue", incoming data will be "latched"
36 into a register and passed out on "outgoing".
38 * if "settrue" is ASSERTED, outgoing is COMBINATORIALLY equal to incoming
39 * on the same cycle that settrue is DEASSERTED, outgoing REMAINS
40 equal (indefinitely) to the incoming value
42 # make reg same as input. reset OK.
43 if isinstance(incoming
, Record
):
44 reg
= Record
.like(incoming
, name
=name
)
46 reg
= Signal
.like(incoming
, name
=name
)
47 m
.d
.comb
+= outgoing
.eq(Mux(settrue
, incoming
, reg
))
48 with m
.If(settrue
): # pass in some kind of expression/condition here
49 m
.d
.sync
+= reg
.eq(incoming
) # latch input into register
53 def mkname(prefix
, suffix
):
56 return "%s_%s" % (prefix
, suffix
)
59 class SRLatch(Elaboratable
):
60 def __init__(self
, sync
=True, llen
=1, name
=None):
63 s_n
, r_n
= mkname("s", name
), mkname("r", name
)
64 q_n
, qn_n
= mkname("q", name
), mkname("qn", name
)
65 qlq_n
= mkname("qlq", name
)
66 self
.s
= Signal(llen
, name
=s_n
, reset
=0)
67 self
.r
= Signal(llen
, name
=r_n
, reset
=(1<<llen
)-1) # defaults to off
68 self
.q
= Signal(llen
, name
=q_n
, reset_less
=True)
69 self
.qn
= Signal(llen
, name
=qn_n
, reset_less
=True)
70 self
.qlq
= Signal(llen
, name
=qlq_n
, reset_less
=True)
72 def elaborate(self
, platform
):
74 q_int
= Signal(self
.llen
)
76 m
.d
.sync
+= q_int
.eq((q_int
& ~self
.r
) | self
.s
)
78 m
.d
.comb
+= self
.q
.eq(q_int
)
80 m
.d
.comb
+= self
.q
.eq((q_int
& ~self
.r
) | self
.s
)
81 m
.d
.comb
+= self
.qn
.eq(~self
.q
)
82 m
.d
.comb
+= self
.qlq
.eq(self
.q | q_int
) # useful output
87 return self
.s
, self
.r
, self
.q
, self
.qn
114 dut
= SRLatch(llen
=4)
115 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
116 with
open("test_srlatch.il", "w") as f
:
119 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch.vcd')
121 dut
= SRLatch(sync
=False, llen
=4)
122 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
123 with
open("test_srlatch_async.il", "w") as f
:
126 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch_async.vcd')
128 if __name__
== '__main__':