src/nmutil/picker.py

   1 """ Priority Picker: optimised back-to-back PriorityEncoder and Decoder
   2     and MultiPriorityPicker: cascading mutually-exclusive pickers
   3
   4     PriorityPicker: the input is N bits, the output is N bits wide and
   5     only one is enabled.
   6
   7     MultiPriorityPicker: likewise except that there are M pickers and
   8     each output is guaranteed mutually exclusive.  Optionally:
   9     an "index" (and enable line) is also outputted.
  10
  11     MultiPriorityPicker is designed for port-selection, when there are
  12     multiple "things" (of width N) contending for access to M "ports".
  13     When the M=0 "thing" requests a port, it gets allocated port 0
  14     (always).  However if the M=0 "thing" does *not* request a port,
  15     this gives the M=1 "thing" the opportunity to gain access to port 0.
  16
  17     Given that N may potentially be much greater than M (16 bits wide
  18     where M may be e.g. only 4) we can't just ok, "ok so M=N therefore
  19     M=0 gets access to port 0, M=1 gets access to port 1" etc.
  20 """
  21
  22 from nmigen import Module, Signal, Cat, Elaboratable, Array, Const, Mux
  23 from nmigen.cli import verilog, rtlil
  24 import math
  25
  26 class PriorityPicker(Elaboratable):
  27     """ implements a priority-picker.  input: N bits, output: N bits
  28     """
  29     def __init__(self, wid):
  30         self.wid = wid
  31         # inputs
  32         self.i = Signal(wid, reset_less=True)
  33         self.o = Signal(wid, reset_less=True)
  34         self.en_o = Signal(reset_less=True) # true if any output is true
  35
  36     def elaborate(self, platform):
  37         m = Module()
  38
  39         # works by saying, "if all previous bits were zero, we get a chance"
  40         res = []
  41         ni = Signal(self.wid, reset_less = True)
  42         m.d.comb += ni.eq(~self.i)
  43         for i in range(0, self.wid):
  44             t = Signal(name="t%d" % i, reset_less = True)
  45             res.append(t)
  46             if i == 0:
  47                 m.d.comb += t.eq(self.i[i])
  48             else:
  49                 m.d.comb += t.eq(~Cat(ni[i], *self.i[:i]).bool())
  50
  51         # we like Cat(*xxx).  turn lists into concatenated bits
  52         m.d.comb += self.o.eq(Cat(*res))
  53         # useful "is any output enabled" signal
  54         m.d.comb += self.en_o.eq(self.o.bool()) # true if 1 input is true
  55
  56         return m
  57
  58     def __iter__(self):
  59         yield self.i
  60         yield self.o
  61
  62     def ports(self):
  63         return list(self)
  64
  65
  66 class MultiPriorityPicker(Elaboratable):
  67     """ implements a multi-input priority picker
  68         Mx inputs of N bits, Mx outputs of N bits, only one is set
  69
  70         Each picker masks out the one below it, such that the first
  71         gets top priority, the second cannot have the same bit that
  72         the first has set, and so on.  To do this, a "mask" accumulates
  73         the output from the chain, masking the input to the next chain.
  74
  75         Also outputted (optional): an index for each picked "thing".
  76     """
  77     def __init__(self, wid, levels, indices=False):
  78         self.levels = levels
  79         self.wid = wid
  80         self.indices = indices
  81
  82         # only the one input, but multiple (single) bit outputs
  83         self.i = Signal(self.wid, reset_less=True)
  84
  85         # create array of (single-bit) outputs (unary)
  86         o_l = [] # array of picker outputs
  87         for j in range(self.levels):
  88             o = Signal(self.wid, name="o_%d" % j, reset_less=True)
  89             o_l.append(o)
  90         self.o = Array(o_l)
  91
  92         if not self.indices:
  93             return
  94
  95         # add an array of "enables" and indices
  96         self.en_o = Signal(self.levels, name="en_o", reset_less=True)
  97         lidx = math.ceil(math.log2(self.levels))
  98         idx_o = [] # store the array of indices
  99         for j in range(self.levels):
 100             i = Signal(lidx, name="idxo_%d" % j, reset_less=True)
 101             idx_o.append(i)
 102         self.idx_o = Array(idx_o)
 103
 104     def elaborate(self, platform):
 105         m = Module()
 106         comb = m.d.comb
 107
 108         # create Priority Pickers, accumulate their outputs and prevent
 109         # the next one in the chain from selecting that output bit.
 110         # the input from the current picker will be "masked" and connected
 111         # to the *next* picker on the next loop
 112         prev_pp = None
 113         p_mask = None
 114         pp_l = []
 115         i = self.i
 116         for j in range(self.levels):
 117             o = self.o[j]
 118             pp = PriorityPicker(self.wid)
 119             pp_l.append(pp)
 120             setattr(m.submodules, "pp%d" % j, pp)
 121             comb += o.eq(pp.o)
 122             if prev_pp is None:
 123                 comb += pp.i.eq(i)
 124                 p_mask = Const(0, self.wid)
 125             else:
 126                 mask = Signal(self.wid, name="m_%d" % j, reset_less=True)
 127                 comb += mask.eq(prev_pp.o | p_mask) # accumulate output bits
 128                 comb += pp.i.eq(i & ~mask)          # mask out input
 129                 p_mask = mask
 130             i = pp.i # for input to next round
 131             prev_pp = pp
 132
 133         if not self.indices:
 134             return m
 135
 136         # for each picker enabled, pass that out and set a cascading index
 137         lidx = math.ceil(math.log2(self.levels))
 138         en_l = []
 139         prev_count = None
 140         for j in range(self.levels):
 141             en_o = pp_l[j].en_o
 142             en_l.append(en_o)
 143             if prev_count is None:
 144                 comb += self.idx_o[j].eq(0)
 145             else:
 146                 count1 = Signal(lidx, name="count_%d" % j, reset_less=True)
 147                 comb += count1.eq(prev_count + Const(1, lidx))
 148                 comb += self.idx_o[j].eq(Mux(en_o, count1, prev_count))
 149             prev_count = self.idx_o[j]
 150
 151         # concat accumulated enable bits
 152         comb += self.en_o.eq(Cat(*en_o))
 153
 154         return m
 155
 156     def __iter__(self):
 157         yield self.i
 158         yield from self.o
 159         if not self.indices:
 160             return
 161         yield self.en_o
 162         yield from self.idx_o
 163
 164     def ports(self):
 165         return list(self)
 166
 167
 168 if __name__ == '__main__':
 169     dut = MultiPriorityPicker(5, 4, True)
 170     vl = rtlil.convert(dut, ports=dut.ports())
 171     with open("test_multi_picker.il", "w") as f:
 172         f.write(vl)