src/openpower/consts.py

   1 # just... don't ask.  MSB0 is a massive pain in the neck.
   2 # this module, aside from creating various field constants,
   3 # helps out by creating alternative (identical) classes with
   4 # a "b" name to indicate "MSB0 big-endian".
   5
   6
   7 # sigh create little-ended versions of bitfield flags
   8 def botchify(bekls, lekls, msb=63):
   9     for attr in dir(bekls):
  10         if attr[0] == '_':
  11             continue
  12         setattr(lekls, attr, msb-getattr(bekls, attr))
  13
  14
  15 # Can't think of a better place to put these functions.
  16 # Return an arbitrary subfield of a larger field.
  17 def field_slice(msb0_start, msb0_end, field_width=64):
  18     """field_slice
  19
  20     Answers with a subfield slice of the signal r ("register"),
  21     where the start and end bits use IBM "MSB 0" conventions.
  22
  23     see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
  24
  25     * assertion: msb0_start < msb0_end.
  26     * The range specified is inclusive on both ends.
  27     * field_width specifies the total number of bits (note: not bits-1)
  28     """
  29     if msb0_start >= msb0_end:
  30         raise ValueError(
  31             "start ({}) must be less than end ({})".format(msb0_start, msb0_end)
  32         )
  33     # sigh.  MSB0 (IBM numbering) is inverted.  converting to python
  34     # we *swap names* so as not to get confused by having "end, start"
  35     lsb0_end = (field_width-1) - msb0_start
  36     lsb0_start = (field_width-1) - msb0_end
  37
  38     return slice(lsb0_start, lsb0_end + 1)
  39
  40
  41 def field(r, msb0_start, msb0_end=None, field_width=64):
  42     """Answers with a subfield of the signal r ("register"), where
  43     the start and end bits use IBM conventions.  start < end, if
  44     end is provided.  The range specified is inclusive on both ends.
  45
  46     Answers with a subfield of the signal r ("register"),
  47     where the start and end bits use IBM "MSB 0" conventions.
  48     If end is not provided, a single bit subfield is returned.
  49
  50     see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
  51
  52     * assertion: msb0_start < msb0_end.
  53     * The range specified is inclusive on both ends.
  54     * field_width specifies the total number of bits (note: not bits-1)
  55
  56     Example usage:
  57
  58         comb += field(insn, 0, 6, field_width=32).eq(17)
  59         # NOTE: NEVER DIRECTLY ACCESS OPCODE FIELDS IN INSTRUCTIONS.
  60         # This example is purely for illustrative purposes only.
  61         # Use self.fields.FormXYZ.etcetc instead.
  62
  63         comb += field(msr, MSRb.TEs, MSRb.TEe).eq(0)
  64
  65     Proof by substitution:
  66
  67            field(insn, 0, 6, field_width=32).eq(17)
  68         == insn[field_slice(0, 6, field_width=32)].eq(17)
  69         == insn[slice((31-6), (31-0)+1)].eq(17)
  70         == insn[slice(25, 32)].eq(17)
  71         == insn[25:32].eq(17)
  72
  73            field(msr, MSRb.TEs, MSRb.TEe).eq(0)
  74         == field(msr, 53, 54).eq(0)
  75         == msr[field_slice(53, 54)].eq(0)
  76         == msr[slice((63-54), (63-53)+1)].eq(0)  # note cross-over!
  77         == msr[slice(9, 11)].eq(0)
  78         == msr[9:11].eq(0)
  79     """
  80     if msb0_end is None:
  81         return r[(field_width - 1) - msb0_start]
  82     else:
  83         return r[field_slice(msb0_start, msb0_end, field_width)]
  84
  85
  86 # Listed in V3.0B Book III Chap 4.2.1
  87 # MSR bit numbers, *bigendian* order (PowerISA format)
  88 # use this in the simulator
  89 class MSRb:
  90     SF  = 0     # Sixty-Four bit mode
  91     HV  = 3     # Hypervisor state
  92     UND = 5     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
  93     TSs = 29    # Transactional State (subfield)
  94     TSe = 30    # Transactional State (subfield)
  95     TM  = 31    # Transactional Memory Available
  96     VEC = 38    # Vector Available
  97     VSX = 40    # VSX Available
  98     S   = 41    # Secure state
  99     EE  = 48    # External interrupt Enable
 100     PR  = 49    # PRoblem state
 101     FP  = 50    # FP available
 102     ME  = 51    # Machine Check int enable
 103     FE0 = 52    # Floating-Point Exception Mode 0
 104     TEs = 53    # Trace Enable (subfield)
 105     TEe = 54    # Trace Enable (subfield)
 106     FE1 = 55    # Floating-Point Exception Mode 1
 107     IR  = 58    # Instruction Relocation
 108     DR  = 59    # Data Relocation
 109     PMM = 60    # Performance Monitor Mark
 110     RI  = 62    # Recoverable Interrupt
 111     LE  = 63    # Little Endian
 112
 113 # use this inside the HDL (where everything is little-endian)
 114 class MSR:
 115     pass
 116
 117 botchify(MSRb, MSR)
 118
 119 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
 120
 121 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
 122 # (TODO: add more?)
 123 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
 124 # to expand traptype to cope with the increased range
 125
 126 # use this in the simulator
 127 class PIb:
 128     INVALID      = 33    # 1 for an invalid mem err
 129     PERMERR      = 35    # 1 for an permanent mem err
 130     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
 131     FP           = 43    # 1 if FP exception
 132     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
 133     PRIV         = 45    # 1 if privileged interrupt
 134     TRAP         = 46    # 1 if exception is "trap" type
 135     ADR          = 47    # 0 if SRR0 = address of instruction causing exception
 136
 137 # and use this in the HDL
 138 class PI:
 139     pass
 140
 141 botchify(PIb, PI)
 142
 143 # see traptype (and trap main_stage.py)
 144 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
 145 # to expand traptype to cope with the increased range
 146
 147 class TT:
 148     FP = 1<<0
 149     PRIV = 1<<1
 150     TRAP = 1<<2
 151     ADDR = 1<<3
 152     EINT = 1<<4  # external interrupt
 153     DEC = 1<<5   # decrement counter
 154     MEMEXC = 1<<6 # LD/ST exception
 155     ILLEG = 1<<7 # currently the max
 156     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
 157     size = 8 # MUST update this to contain the full number of Trap Types
 158
 159
 160 # EXTRA3 3-bit subfield (spec)
 161 class SPECb:
 162     VEC = 0  # 1 for vector, 0 for scalar
 163     MSB = 1  # augmented register number, MSB
 164     LSB = 2  # augmented register number, LSB
 165
 166
 167 SPEC_SIZE = 3
 168 SPEC_AUG_SIZE = 2  # augmented subfield size (MSB+LSB above)
 169 class SPEC:
 170     pass
 171 botchify(SPECb, SPEC, SPEC_SIZE-1)
 172
 173
 174 # EXTRA field, with EXTRA2 subfield encoding
 175 class EXTRA2b:
 176     IDX0_VEC = 0
 177     IDX0_MSB = 1
 178     IDX1_VEC = 2
 179     IDX1_MSB = 3
 180     IDX2_VEC = 4
 181     IDX2_MSB = 5
 182     IDX3_VEC = 6
 183     IDX3_MSB = 7
 184     RESERVED = 8
 185
 186
 187 EXTRA2_SIZE = 9
 188 class EXTRA2:
 189     pass
 190 botchify(EXTRA2b, EXTRA2, EXTRA2_SIZE-1)
 191
 192
 193 # EXTRA field, with EXTRA3 subfield encoding
 194 class EXTRA3:
 195     IDX0 = [0, 1, 2]
 196     IDX1 = [3, 4, 5]
 197     IDX2 = [6, 7, 8]
 198     MASK = [6, 7, 8]
 199
 200
 201 EXTRA3_SIZE = 9
 202
 203
 204 # SVP64 ReMapped Field (from v3.1 EXT001 Prefix)
 205 class SVP64P:
 206     OPC = range(0, 6)
 207     SVP64_7_9 = [7, 9]
 208     RM = [6, 8] + list(range(10, 32))
 209
 210 # 24 bits in RM
 211 SVP64P_SIZE = 24
 212
 213
 214 # CR SVP64 offsets
 215 class SVP64CROffs:
 216     CR0 = 0    # TODO: increase when CRs are expanded to 128
 217     CR1 = 1    # TODO: increase when CRs are expanded to 128
 218     CRPred = 4 # TODO: increase when CRs are expanded to 128
 219
 220
 221 class SVP64MODEb:
 222     # mode bits
 223     MOD2_MSB = 0
 224     MOD2_LSB = 1
 225     LDST_BITREV = 2 # set =1 for bitreverse mode
 226     # when predicate not set: 0=ignore/skip 1=zero
 227     DZ = 3  # for destination
 228     SZ = 4  # for source
 229     # reduce mode
 230     REDUCE = 2  # 0=normal predication 1=reduce mode
 231     PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
 232     SVM = 3  # subvector reduce mode 0=independent 1=horizontal
 233     CRM = 4  # CR mode on reduce (Rc=1) 0=some 1=all
 234     RG = 4   # Reverse-gear on reduce
 235     # saturation mode
 236     N = 2  # saturation signed mode 0=signed 1=unsigned
 237     # ffirst and predicate result modes
 238     INV = 2  # invert CR sense 0=set 1=unset
 239     CR_MSB = 3  # CR bit to update (with Rc=1)
 240     CR_LSB = 4
 241     RC1 = 4  # update CR as if Rc=1 (when Rc=0)
 242     # LD immediate els (element-stride) locations, depending on mode
 243     ELS_NORMAL = 4
 244     ELS_FFIRST_PRED = 3
 245     ELS_SAT = 4
 246     # BO bits
 247     BO_MSB = 2
 248     BO_LSB = 4
 249
 250
 251 SVP64MODE_SIZE = 5
 252
 253
 254 class SVP64MODE:
 255     pass
 256
 257
 258 botchify(SVP64MODEb, SVP64MODE, SVP64MODE_SIZE-1)
 259
 260 # add subfields to use with nmutil.sel
 261 SVP64MODE.MOD2 = [0, 1]
 262 SVP64MODE.CR = [3, 4]
 263
 264
 265 # CR sub-fields
 266 class CRb:
 267     LT = 0
 268     GT = 1
 269     EQ = 2
 270     SO = 3
 271
 272
 273 CR_SIZE = 4
 274
 275
 276 class CR:
 277     pass
 278
 279
 280 botchify(CRb, CR, CR_SIZE-1)
 281
 282
 283 # POWER9 Register Files
 284 # XXX these are specific to Libre-SOC's decoder. really, they
 285 # should be in libre-soc.  however... long story: because the
 286 # PowerDecoder2 has been moved to openpower-isa, and its decoding
 287 # depends on that, then... whoops.
 288
 289 # "State" Regfile
 290 class StateRegsEnum:
 291     PC = 0
 292     MSR = 1
 293     SVSTATE = 2
 294     N_REGS = 3 # maximum number of regs
 295
 296 # Fast SPRs Regfile
 297 class FastRegsEnum:
 298     CTR = 0
 299     LR = 1
 300     TAR = 2
 301     SRR0 = 3
 302     SRR1 = 4
 303     XER = 5 # non-XER bits
 304     DEC = 6
 305     TB = 7
 306     SVSRR0 = 8
 307     N_REGS = 9 # maximum number of regs
 308
 309 # XER Regfile
 310 class XERRegsEnum:
 311     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 312     CA=1 # CA and CA32
 313     OV=2 # OV and OV32
 314     N_REGS = 3 # maximum number of regs