src/openpower/decoder/decode2execute1.py

   1 """Decode2ToExecute1Type
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Signal, Record
   7 from nmutil.iocontrol import RecordObject
   8 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
   9                                      SPRfull, SPRreduced, LDSTMode)
  10 from openpower.consts import TT
  11 from openpower.exceptions import LDSTException
  12
  13
  14 class Data(Record):
  15
  16     def __init__(self, width, name):
  17         name_ok = "%s_ok" % name
  18         layout = ((name, width), (name_ok, 1))
  19         Record.__init__(self, layout)
  20         self.data = getattr(self, name) # convenience
  21         self.ok = getattr(self, name_ok) # convenience
  22         self.data.reset_less = True # grrr
  23         self.reset_less = True # grrr
  24
  25     def ports(self):
  26         return [self.data, self.ok]
  27
  28
  29 class IssuerDecode2ToOperand(RecordObject):
  30     """IssuerDecode2ToOperand
  31
  32     contains the subset of fields needed for Issuer to decode the instruction
  33     and get register rdflags signals set up.  it also doubles up as the
  34     "Trap" temporary store, because part of the Decoder's job is to
  35     identify whether a trap / interrupt / exception should occur.
  36     """
  37
  38     def __init__(self, name=None):
  39
  40         RecordObject.__init__(self, name=name)
  41
  42         # current "state" (TODO: this in its own Record)
  43         self.msr = Signal(64, reset_less=True)
  44         self.cia = Signal(64, reset_less=True)
  45         self.svstate = Signal(32, reset_less=True)
  46
  47         # instruction, type and decoded information
  48         self.insn = Signal(32, reset_less=True) # original instruction
  49         self.insn_type = Signal(MicrOp, reset_less=True)
  50         self.fn_unit = Signal(Function, reset_less=True)
  51         self.lk = Signal(reset_less=True)
  52         self.rc = Data(1, "rc")
  53         self.oe = Data(1, "oe")
  54         self.input_carry = Signal(CryIn, reset_less=True)
  55         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
  56         self.ldst_exc  = LDSTException("exc")
  57         self.trapaddr  = Signal(13, reset_less=True)
  58         self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
  59         self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
  60         self.is_32bit = Signal(reset_less=True)
  61
  62
  63 class Decode2ToOperand(IssuerDecode2ToOperand):
  64
  65     def __init__(self, name=None):
  66
  67         IssuerDecode2ToOperand.__init__(self, name=name)
  68
  69         # instruction, type and decoded information
  70         self.imm_data = Data(64, name="imm")
  71         self.invert_in = Signal(reset_less=True)
  72         self.zero_a = Signal(reset_less=True)
  73         self.output_carry = Signal(reset_less=True)
  74         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
  75         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
  76         self.invert_out = Signal(reset_less=True)
  77         self.is_32bit = Signal(reset_less=True)
  78         self.is_signed = Signal(reset_less=True)
  79         self.data_len = Signal(4, reset_less=True) # bytes
  80         self.byte_reverse  = Signal(reset_less=True)
  81         self.sign_extend  = Signal(reset_less=True)# do we need this?
  82         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
  83         self.write_cr0 = Signal(reset_less=True)
  84
  85
  86 class Decode2ToExecute1Type(RecordObject):
  87
  88     def __init__(self, name=None, asmcode=True, opkls=None, do=None,
  89                        regreduce_en=False):
  90
  91         if regreduce_en:
  92             SPR = SPRreduced
  93         else:
  94             SPR = SPRfull
  95
  96         if do is None and opkls is None:
  97             opkls = Decode2ToOperand
  98
  99         RecordObject.__init__(self, name=name)
 100
 101         if asmcode:
 102             self.asmcode = Signal(8, reset_less=True) # only for simulator
 103         self.write_reg = Data(7, name="rego")
 104         self.write_ea = Data(7, name="ea") # for LD/ST in update mode
 105         self.read_reg1 = Data(7, name="reg1")
 106         self.read_reg2 = Data(7, name="reg2")
 107         self.read_reg3 = Data(7, name="reg3")
 108         self.write_spr = Data(SPR, name="spro")
 109         self.read_spr1 = Data(SPR, name="spr1")
 110         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
 111
 112         self.xer_in = Signal(3, reset_less=True)   # xer might be read
 113         self.xer_out = Signal(reset_less=True)  # xer might be written
 114
 115         # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
 116         self.read_fast1 = Data(3, name="fast1")
 117         self.read_fast2 = Data(3, name="fast2")
 118         self.read_fast3 = Data(3, name="fast3")   # really only for SVSRR0
 119         self.write_fast1 = Data(3, name="fasto1")
 120         self.write_fast2 = Data(3, name="fasto2")
 121         self.write_fast3 = Data(3, name="fasto3") # likewise
 122
 123         self.read_cr1 = Data(7, name="cr_in1")
 124         self.read_cr2 = Data(7, name="cr_in2")
 125         self.read_cr3 = Data(7, name="cr_in2")
 126         self.write_cr = Data(7, name="cr_out")
 127
 128         # decode operand data
 129         print ("decode2execute init", name, opkls, do)
 130         #assert name is not None, str(opkls)
 131         if do is not None:
 132             self.do = do
 133         else:
 134             self.do = opkls(name)