src/openpower/decoder/decode2execute1.py

   1 """Decode2ToExecute1Type
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Signal, Record
   7 from nmutil.iocontrol import RecordObject
   8 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
   9                                      SPRfull, SPRreduced, LDSTMode)
  10 from openpower.consts import TT
  11 from openpower.exceptions import LDSTException
  12 from openpower.decoder.power_svp64_rm import sv_input_record_layout
  13 from openpower.decoder.power_enums import asmlen
  14
  15 from openpower.util import log
  16
  17
  18 class Data(Record):
  19
  20     def __init__(self, width, name):
  21         name_ok = "%s_ok" % name
  22         layout = ((name, width), (name_ok, 1))
  23         Record.__init__(self, layout)
  24         self.data = getattr(self, name) # convenience
  25         self.ok = getattr(self, name_ok) # convenience
  26         self.data.reset_less = True # grrr
  27         self.reset_less = True # grrr
  28
  29     def ports(self):
  30         return [self.data, self.ok]
  31
  32
  33 class SVP64Reg(Record):
  34
  35     def __init__(self, width, name):
  36         name_ok = "%s_ok" % name
  37         name_offs = "%s_offs" % name
  38         name_base = "%s_base" % name
  39         layout = ((name, width), (name_offs, width),
  40                   (name_base, width), (name_ok, 1))
  41         Record.__init__(self, layout)
  42         self.data = getattr(self, name) # convenience
  43         self.base = getattr(self, name_base) # convenience
  44         self.offs = getattr(self, name_offs) # convenience
  45         self.ok = getattr(self, name_ok) # convenience
  46         self.data.reset_less = True # grrr
  47         self.reset_less = True # grrr
  48
  49     def ports(self):
  50         return [self.data, self.ok]
  51
  52
  53 class IssuerDecode2ToOperand(RecordObject):
  54     """IssuerDecode2ToOperand
  55
  56     contains the subset of fields needed for Issuer to decode the instruction
  57     and get register rdflags signals set up.  it also doubles up as the
  58     "Trap" temporary store, because part of the Decoder's job is to
  59     identify whether a trap / interrupt / exception should occur.
  60     """
  61
  62     def __init__(self, name=None):
  63
  64         RecordObject.__init__(self, layout=sv_input_record_layout,
  65                                     name=name)
  66
  67         # current "state" (TODO: this in its own Record)
  68         self.msr = Signal(64, reset_less=True)
  69         self.cia = Signal(64, reset_less=True)
  70         self.svstate = Signal(64, reset_less=True)
  71
  72         # instruction, type and decoded information
  73         self.insn = Signal(32, reset_less=True) # original instruction
  74         self.insn_type = Signal(MicrOp, reset_less=True)
  75         self.fn_unit = Signal(Function, reset_less=True)
  76         self.lk = Signal(reset_less=True)
  77         self.rc = Data(1, "rc")
  78         self.oe = Data(1, "oe")
  79         self.input_carry = Signal(CryIn, reset_less=True)
  80         self.output_carry = Signal(reset_less=True)
  81         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
  82         self.ldst_exc  = LDSTException("exc")
  83         self.trapaddr  = Signal(13, reset_less=True)
  84         self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
  85         self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
  86         self.is_32bit = Signal(reset_less=True)
  87
  88
  89 class Decode2ToOperand(IssuerDecode2ToOperand):
  90
  91     def __init__(self, name=None):
  92
  93         IssuerDecode2ToOperand.__init__(self, name=name)
  94
  95         # instruction, type and decoded information
  96         self.imm_data = Data(64, name="imm")
  97         self.invert_in = Signal(reset_less=True)
  98         self.zero_a = Signal(reset_less=True)
  99         self.output_carry = Signal(reset_less=True)
 100         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 101         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 102         self.invert_out = Signal(reset_less=True)
 103         self.is_32bit = Signal(reset_less=True)
 104         self.is_signed = Signal(reset_less=True)
 105         self.data_len = Signal(4, reset_less=True) # bytes
 106         self.byte_reverse  = Signal(reset_less=True)
 107         self.reserve  = Signal(reset_less=True) # atomic update ldarx/stdcx etc
 108         self.sign_extend  = Signal(reset_less=True)# do we need this?
 109         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
 110         self.write_cr0 = Signal(reset_less=True)
 111
 112
 113 class Decode2ToExecute1Type(RecordObject):
 114
 115     def __init__(self, name=None, asmcode=True, opkls=None, do=None,
 116                        regreduce_en=False):
 117
 118         if regreduce_en:
 119             SPR = SPRreduced
 120         else:
 121             SPR = SPRfull
 122
 123         if do is None and opkls is None:
 124             opkls = Decode2ToOperand
 125
 126         RecordObject.__init__(self, name=name)
 127
 128         if asmcode:
 129             self.asmcode = Signal(asmlen, reset_less=True) # only for simulator
 130         self.write_reg = SVP64Reg(7, name="rego")
 131         self.write_ea = SVP64Reg(7, name="ea") # for LD/ST in update mode
 132         self.read_reg1 = SVP64Reg(7, name="reg1")
 133         self.read_reg2 = SVP64Reg(7, name="reg2")
 134         self.read_reg3 = SVP64Reg(7, name="reg3")
 135         self.write_spr = Data(SPR, name="spro")
 136         self.read_spr1 = Data(SPR, name="spr1")
 137         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
 138
 139         self.xer_in = Signal(3, reset_less=True)   # xer might be read
 140         self.xer_out = Signal(reset_less=True)  # xer might be written
 141
 142         # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
 143         self.read_fast1 = Data(4, name="fast1")
 144         self.read_fast2 = Data(4, name="fast2")
 145         self.read_fast3 = Data(4, name="fast3")   # really only for SVSRR0
 146         self.write_fast1 = Data(4, name="fasto1")
 147         self.write_fast2 = Data(4, name="fasto2")
 148         self.write_fast3 = Data(4, name="fasto3") # likewise
 149         # and STATE regs (DEC, TB)
 150         self.read_state1 = Data(3, name="state1")  # really only for DEC/TB
 151         self.write_state1 = Data(3, name="state1")
 152
 153         self.read_cr1 = Data(7, name="cr_in1")
 154         self.read_cr2 = Data(7, name="cr_in2")
 155         self.read_cr3 = Data(7, name="cr_in3")
 156         self.write_cr = Data(7, name="cr_out")
 157
 158         # decode operand data
 159         log ("decode2execute init", name, opkls, do)
 160         #assert name is not None, str(opkls)
 161         if do is not None:
 162             self.do = do
 163         else:
 164             self.do = opkls(name)