src/openpower/decoder/decode2execute1.py

   1 """Decode2ToExecute1Type
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Signal, Record
   7 from nmutil.iocontrol import RecordObject
   8 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
   9                                      SPRfull, SPRreduced, LDSTMode)
  10 from openpower.consts import TT
  11 from openpower.exceptions import LDSTException
  12 from openpower.decoder.power_svp64_rm import sv_input_record_layout
  13 from openpower.decoder.power_enums import asmlen
  14
  15 from openpower.util import log
  16
  17
  18 class Data(Record):
  19
  20     def __init__(self, width, name):
  21         name_ok = "%s_ok" % name
  22         layout = ((name, width), (name_ok, 1))
  23         Record.__init__(self, layout)
  24         self.data = getattr(self, name) # convenience
  25         self.ok = getattr(self, name_ok) # convenience
  26         self.data.reset_less = True # grrr
  27         self.reset_less = True # grrr
  28
  29     def ports(self):
  30         return [self.data, self.ok]
  31
  32
  33 class IssuerDecode2ToOperand(RecordObject):
  34     """IssuerDecode2ToOperand
  35
  36     contains the subset of fields needed for Issuer to decode the instruction
  37     and get register rdflags signals set up.  it also doubles up as the
  38     "Trap" temporary store, because part of the Decoder's job is to
  39     identify whether a trap / interrupt / exception should occur.
  40     """
  41
  42     def __init__(self, name=None):
  43
  44         RecordObject.__init__(self, layout=sv_input_record_layout,
  45                                     name=name)
  46
  47         # current "state" (TODO: this in its own Record)
  48         self.msr = Signal(64, reset_less=True)
  49         self.cia = Signal(64, reset_less=True)
  50         self.svstate = Signal(64, reset_less=True)
  51
  52         # instruction, type and decoded information
  53         self.insn = Signal(32, reset_less=True) # original instruction
  54         self.insn_type = Signal(MicrOp, reset_less=True)
  55         self.fn_unit = Signal(Function, reset_less=True)
  56         self.lk = Signal(reset_less=True)
  57         self.rc = Data(1, "rc")
  58         self.oe = Data(1, "oe")
  59         self.input_carry = Signal(CryIn, reset_less=True)
  60         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
  61         self.ldst_exc  = LDSTException("exc")
  62         self.trapaddr  = Signal(13, reset_less=True)
  63         self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
  64         self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
  65         self.is_32bit = Signal(reset_less=True)
  66
  67
  68 class Decode2ToOperand(IssuerDecode2ToOperand):
  69
  70     def __init__(self, name=None):
  71
  72         IssuerDecode2ToOperand.__init__(self, name=name)
  73
  74         # instruction, type and decoded information
  75         self.imm_data = Data(64, name="imm")
  76         self.invert_in = Signal(reset_less=True)
  77         self.zero_a = Signal(reset_less=True)
  78         self.output_carry = Signal(reset_less=True)
  79         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
  80         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
  81         self.invert_out = Signal(reset_less=True)
  82         self.is_32bit = Signal(reset_less=True)
  83         self.is_signed = Signal(reset_less=True)
  84         self.data_len = Signal(4, reset_less=True) # bytes
  85         self.byte_reverse  = Signal(reset_less=True)
  86         self.sign_extend  = Signal(reset_less=True)# do we need this?
  87         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
  88         self.write_cr0 = Signal(reset_less=True)
  89
  90
  91 class Decode2ToExecute1Type(RecordObject):
  92
  93     def __init__(self, name=None, asmcode=True, opkls=None, do=None,
  94                        regreduce_en=False):
  95
  96         if regreduce_en:
  97             SPR = SPRreduced
  98         else:
  99             SPR = SPRfull
 100
 101         if do is None and opkls is None:
 102             opkls = Decode2ToOperand
 103
 104         RecordObject.__init__(self, name=name)
 105
 106         if asmcode:
 107             self.asmcode = Signal(asmlen, reset_less=True) # only for simulator
 108         self.write_reg = Data(7, name="rego")
 109         self.write_ea = Data(7, name="ea") # for LD/ST in update mode
 110         self.read_reg1 = Data(7, name="reg1")
 111         self.read_reg2 = Data(7, name="reg2")
 112         self.read_reg3 = Data(7, name="reg3")
 113         self.write_spr = Data(SPR, name="spro")
 114         self.read_spr1 = Data(SPR, name="spr1")
 115         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
 116
 117         self.xer_in = Signal(3, reset_less=True)   # xer might be read
 118         self.xer_out = Signal(reset_less=True)  # xer might be written
 119
 120         # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
 121         self.read_fast1 = Data(3, name="fast1")
 122         self.read_fast2 = Data(3, name="fast2")
 123         self.read_fast3 = Data(3, name="fast3")   # really only for SVSRR0
 124         self.write_fast1 = Data(3, name="fasto1")
 125         self.write_fast2 = Data(3, name="fasto2")
 126         self.write_fast3 = Data(3, name="fasto3") # likewise
 127
 128         self.read_cr1 = Data(7, name="cr_in1")
 129         self.read_cr2 = Data(7, name="cr_in2")
 130         self.read_cr3 = Data(7, name="cr_in2")
 131         self.write_cr = Data(7, name="cr_out")
 132
 133         # decode operand data
 134         log ("decode2execute init", name, opkls, do)
 135         #assert name is not None, str(opkls)
 136         if do is not None:
 137             self.do = do
 138         else:
 139             self.do = opkls(name)