1 """Decode2ToExecute1Type
3 based on Anton Blanchard microwatt decode2.vhdl
6 from nmigen
import Signal
, Record
7 from nmutil
.iocontrol
import RecordObject
8 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
9 SPRfull
, SPRreduced
, LDSTMode
)
10 from openpower
.consts
import TT
11 from openpower
.exceptions
import LDSTException
12 from openpower
.decoder
.power_svp64_rm
import sv_input_record_layout
17 def __init__(self
, width
, name
):
18 name_ok
= "%s_ok" % name
19 layout
= ((name
, width
), (name_ok
, 1))
20 Record
.__init
__(self
, layout
)
21 self
.data
= getattr(self
, name
) # convenience
22 self
.ok
= getattr(self
, name_ok
) # convenience
23 self
.data
.reset_less
= True # grrr
24 self
.reset_less
= True # grrr
27 return [self
.data
, self
.ok
]
30 class IssuerDecode2ToOperand(RecordObject
):
31 """IssuerDecode2ToOperand
33 contains the subset of fields needed for Issuer to decode the instruction
34 and get register rdflags signals set up. it also doubles up as the
35 "Trap" temporary store, because part of the Decoder's job is to
36 identify whether a trap / interrupt / exception should occur.
39 def __init__(self
, name
=None):
41 RecordObject
.__init
__(self
, layout
=sv_input_record_layout
,
44 # current "state" (TODO: this in its own Record)
45 self
.msr
= Signal(64, reset_less
=True)
46 self
.cia
= Signal(64, reset_less
=True)
47 self
.svstate
= Signal(32, reset_less
=True)
49 # instruction, type and decoded information
50 self
.insn
= Signal(32, reset_less
=True) # original instruction
51 self
.insn_type
= Signal(MicrOp
, reset_less
=True)
52 self
.fn_unit
= Signal(Function
, reset_less
=True)
53 self
.lk
= Signal(reset_less
=True)
54 self
.rc
= Data(1, "rc")
55 self
.oe
= Data(1, "oe")
56 self
.input_carry
= Signal(CryIn
, reset_less
=True)
57 self
.traptype
= Signal(TT
.size
, reset_less
=True) # trap main_stage.py
58 self
.ldst_exc
= LDSTException("exc")
59 self
.trapaddr
= Signal(13, reset_less
=True)
60 self
.read_cr_whole
= Data(8, "cr_rd") # CR full read mask
61 self
.write_cr_whole
= Data(8, "cr_wr") # CR full write mask
62 self
.is_32bit
= Signal(reset_less
=True)
65 class Decode2ToOperand(IssuerDecode2ToOperand
):
67 def __init__(self
, name
=None):
69 IssuerDecode2ToOperand
.__init
__(self
, name
=name
)
71 # instruction, type and decoded information
72 self
.imm_data
= Data(64, name
="imm")
73 self
.invert_in
= Signal(reset_less
=True)
74 self
.zero_a
= Signal(reset_less
=True)
75 self
.output_carry
= Signal(reset_less
=True)
76 self
.input_cr
= Signal(reset_less
=True) # instr. has a CR as input
77 self
.output_cr
= Signal(reset_less
=True) # instr. has a CR as output
78 self
.invert_out
= Signal(reset_less
=True)
79 self
.is_32bit
= Signal(reset_less
=True)
80 self
.is_signed
= Signal(reset_less
=True)
81 self
.data_len
= Signal(4, reset_less
=True) # bytes
82 self
.byte_reverse
= Signal(reset_less
=True)
83 self
.sign_extend
= Signal(reset_less
=True)# do we need this?
84 self
.ldst_mode
= Signal(LDSTMode
, reset_less
=True) # LD/ST mode
85 self
.write_cr0
= Signal(reset_less
=True)
88 class Decode2ToExecute1Type(RecordObject
):
90 def __init__(self
, name
=None, asmcode
=True, opkls
=None, do
=None,
98 if do
is None and opkls
is None:
99 opkls
= Decode2ToOperand
101 RecordObject
.__init
__(self
, name
=name
)
104 self
.asmcode
= Signal(8, reset_less
=True) # only for simulator
105 self
.write_reg
= Data(7, name
="rego")
106 self
.write_ea
= Data(7, name
="ea") # for LD/ST in update mode
107 self
.read_reg1
= Data(7, name
="reg1")
108 self
.read_reg2
= Data(7, name
="reg2")
109 self
.read_reg3
= Data(7, name
="reg3")
110 self
.write_spr
= Data(SPR
, name
="spro")
111 self
.read_spr1
= Data(SPR
, name
="spr1")
112 #self.read_spr2 = Data(SPR, name="spr2") # only one needed
114 self
.xer_in
= Signal(3, reset_less
=True) # xer might be read
115 self
.xer_out
= Signal(reset_less
=True) # xer might be written
117 # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
118 self
.read_fast1
= Data(3, name
="fast1")
119 self
.read_fast2
= Data(3, name
="fast2")
120 self
.read_fast3
= Data(3, name
="fast3") # really only for SVSRR0
121 self
.write_fast1
= Data(3, name
="fasto1")
122 self
.write_fast2
= Data(3, name
="fasto2")
123 self
.write_fast3
= Data(3, name
="fasto3") # likewise
125 self
.read_cr1
= Data(7, name
="cr_in1")
126 self
.read_cr2
= Data(7, name
="cr_in2")
127 self
.read_cr3
= Data(7, name
="cr_in2")
128 self
.write_cr
= Data(7, name
="cr_out")
130 # decode operand data
131 print ("decode2execute init", name
, opkls
, do
)
132 #assert name is not None, str(opkls)
136 self
.do
= opkls(name
)