1 from nmigen
import Module
, Signal
, Elaboratable
, Cat
, Repl
2 from nmigen
.asserts
import Assert
, AnyConst
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import create_pdecode
, PowerOp
6 from soc
.decoder
.power_enums
import (In1Sel
, In2Sel
, In3Sel
,
9 from soc
.decoder
.power_decoder2
import (PowerDecode2
,
10 Decode2ToExecute1Type
)
13 class Driver(Elaboratable
):
17 self
.instruction
= None
19 def elaborate(self
, platform
):
21 self
.comb
= self
.m
.d
.comb
22 self
.instruction
= Signal(32)
24 self
.comb
+= self
.instruction
.eq(AnyConst(32))
26 pdecode
= create_pdecode()
28 self
.m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
29 self
.comb
+= pdecode2
.dec
.bigendian
.eq(1) # XXX TODO: bigendian=0
30 self
.comb
+= pdecode2
.dec
.raw_opcode_in
.eq(self
.instruction
)
32 self
.test_in1(pdecode2
, pdecode
)
34 self
.test_in2_fields()
38 self
.test_single_bits()
42 def test_in1(self
, pdecode2
, pdecode
):
45 ra
= self
.instr_bits(11, 15)
46 with m
.If(pdecode
.op
.in1_sel
== In1Sel
.RA
):
47 comb
+= Assert(pdecode2
.e
.read_reg1
.data
== ra
)
48 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 1)
49 with m
.If(pdecode
.op
.in1_sel
== In1Sel
.RA_OR_ZERO
):
51 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 0)
53 comb
+= Assert(pdecode2
.e
.read_reg1
.data
== ra
)
54 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 1)
55 op
= pdecode
.op
.internal_op
56 with m
.If((op
== MicrOp
.OP_BC
) |
57 (op
== MicrOp
.OP_BCREG
)):
58 with m
.If(~self
.instr_bits(8)):
59 comb
+= Assert(pdecode2
.e
.read_spr1
.data
== SPR
.CTR
)
60 comb
+= Assert(pdecode2
.e
.read_spr1
.ok
== 1)
61 with m
.If((op
== MicrOp
.OP_MFSPR
) |
62 (op
== MicrOp
.OP_MTSPR
)):
63 comb
+= Assert(pdecode2
.e
.read_spr1
.data
== self
.instr_bits(11, 20))
64 comb
+= Assert(pdecode2
.e
.read_spr1
.ok
== 1)
69 pdecode2
= m
.submodules
.pdecode2
71 with m
.If(dec
.op
.in2_sel
== In2Sel
.RB
):
72 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 1)
73 comb
+= Assert(pdecode2
.e
.read_reg2
.data
== dec
.RB
)
74 with m
.Elif(dec
.op
.in2_sel
== In2Sel
.NONE
):
75 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 0)
76 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 0)
77 with m
.Elif(dec
.op
.in2_sel
== In2Sel
.SPR
):
78 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 0)
79 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 0)
80 comb
+= Assert(pdecode2
.e
.read_spr2
.ok
== 1)
81 with m
.If(dec
.fields
.FormXL
.XO
[9]):
82 comb
+= Assert(pdecode2
.e
.read_spr2
.data
== SPR
.CTR
)
84 comb
+= Assert(pdecode2
.e
.read_spr2
.data
== SPR
.LR
)
86 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 1)
87 with m
.Switch(dec
.op
.in2_sel
):
88 with m
.Case(In2Sel
.CONST_UI
):
89 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.UI
)
90 with m
.Case(In2Sel
.CONST_SI
):
91 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
92 self
.exts(dec
.SI
, 16, 64))
93 with m
.Case(In2Sel
.CONST_UI_HI
):
94 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.UI
<< 16))
95 with m
.Case(In2Sel
.CONST_SI_HI
):
96 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
97 self
.exts(dec
.SI
<< 16, 32, 64))
98 with m
.Case(In2Sel
.CONST_LI
):
99 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.LI
<< 2))
100 with m
.Case(In2Sel
.CONST_BD
):
101 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.BD
<< 2))
102 with m
.Case(In2Sel
.CONST_DS
):
103 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.DS
<< 2))
104 with m
.Case(In2Sel
.CONST_M1
):
105 comb
+= Assert(pdecode2
.e
.imm_data
.data
== ~
0)
106 with m
.Case(In2Sel
.CONST_SH
):
107 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.sh
)
108 with m
.Case(In2Sel
.CONST_SH32
):
109 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.SH32
)
113 def exts(self
, exts_data
, width
, fullwidth
):
114 exts_data
= exts_data
[0:width
]
115 topbit
= exts_data
[-1]
116 signbits
= Repl(topbit
, fullwidth
-width
)
117 return Cat(exts_data
, signbits
)
119 def test_in2_fields(self
):
122 dec
= m
.submodules
.pdecode2
.dec
124 comb
+= Assert(dec
.RB
== self
.instr_bits(16, 20))
125 comb
+= Assert(dec
.UI
== self
.instr_bits(16, 31))
126 comb
+= Assert(dec
.SI
== self
.instr_bits(16, 31))
127 comb
+= Assert(dec
.LI
== self
.instr_bits(6, 29))
128 comb
+= Assert(dec
.BD
== self
.instr_bits(16, 29))
129 comb
+= Assert(dec
.DS
== self
.instr_bits(16, 29))
130 comb
+= Assert(dec
.sh
== Cat(self
.instr_bits(16, 20),
131 self
.instr_bits(30)))
132 comb
+= Assert(dec
.SH32
== self
.instr_bits(16, 20))
137 pdecode2
= m
.submodules
.pdecode2
138 with m
.If(pdecode2
.dec
.op
.in3_sel
== In3Sel
.RS
):
139 comb
+= Assert(pdecode2
.e
.read_reg3
.ok
== 1)
140 comb
+= Assert(pdecode2
.e
.read_reg3
.data
== self
.instr_bits(6,10))
145 pdecode2
= m
.submodules
.pdecode2
146 sel
= pdecode2
.dec
.op
.out_sel
148 with m
.If(sel
== OutSel
.SPR
):
149 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 1)
150 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 0)
151 with m
.Elif(sel
== OutSel
.NONE
):
152 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 0)
153 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 0)
155 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 0)
156 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 1)
157 data
= pdecode2
.e
.write_reg
.data
158 with m
.If(sel
== OutSel
.RT
):
159 comb
+= Assert(data
== self
.instr_bits(6, 10))
160 with m
.If(sel
== OutSel
.RA
):
161 comb
+= Assert(data
== self
.instr_bits(11, 15))
166 pdecode2
= m
.submodules
.pdecode2
167 sel
= pdecode2
.dec
.op
.rc_sel
169 comb
+= Assert(pdecode2
.e
.rc
.ok
== 1)
170 with m
.If(sel
== RC
.NONE
):
171 comb
+= Assert(pdecode2
.e
.rc
.data
== 0)
172 with m
.If(sel
== RC
.ONE
):
173 comb
+= Assert(pdecode2
.e
.rc
.data
== 1)
174 with m
.If(sel
== RC
.RC
):
175 comb
+= Assert(pdecode2
.e
.rc
.data
== dec
.Rc
)
176 comb
+= Assert(pdecode2
.e
.oe
.ok
== 1)
177 comb
+= Assert(pdecode2
.e
.oe
.data
== dec
.OE
)
179 def test_single_bits(self
):
182 pdecode2
= m
.submodules
.pdecode2
185 comb
+= Assert(e
.invert_in
== dec
.op
.inv_a
)
186 comb
+= Assert(e
.invert_out
== dec
.op
.inv_out
)
187 comb
+= Assert(e
.input_carry
== dec
.op
.cry_in
)
188 comb
+= Assert(e
.output_carry
== dec
.op
.cry_out
)
189 comb
+= Assert(e
.is_32bit
== dec
.op
.is_32b
)
190 comb
+= Assert(e
.is_signed
== dec
.op
.sgn
)
191 with m
.If(dec
.op
.lk
):
192 comb
+= Assert(e
.lk
== self
.instr_bits(31))
193 comb
+= Assert(e
.byte_reverse
== dec
.op
.br
)
194 comb
+= Assert(e
.sign_extend
== dec
.op
.sgn_ext
)
195 comb
+= Assert(e
.update
== dec
.op
.upd
)
196 comb
+= Assert(e
.input_cr
== dec
.op
.cr_in
)
197 comb
+= Assert(e
.output_cr
== dec
.op
.cr_out
)
199 def instr_bits(self
, start
, end
=None):
202 return self
.instruction
[::-1][start
:end
+1][::-1]
205 class Decoder2TestCase(FHDLTestCase
):
206 def test_decoder2(self
):
208 self
.assertFormal(module
, mode
="bmc", depth
=4)
210 if __name__
== '__main__':