1 from nmigen
import Module
, Signal
, Elaboratable
, Cat
, Repl
2 from nmigen
.asserts
import Assert
, AnyConst
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.power_decoder
import create_pdecode
, PowerOp
6 from openpower
.decoder
.power_enums
import (In1Sel
, In2Sel
, In3Sel
,
8 MicrOp
, SPRfull
as SPR
)
9 from openpower
.decoder
.power_decoder2
import (PowerDecode2
,
10 Decode2ToExecute1Type
)
14 class Driver(Elaboratable
):
18 self
.instruction
= None
20 def elaborate(self
, platform
):
22 self
.comb
= self
.m
.d
.comb
23 self
.instruction
= Signal(32)
25 self
.comb
+= self
.instruction
.eq(AnyConst(32))
27 pdecode
= create_pdecode()
29 self
.m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
30 self
.comb
+= pdecode2
.dec
.bigendian
.eq(1) # XXX TODO: bigendian=0
31 self
.comb
+= pdecode2
.dec
.raw_opcode_in
.eq(self
.instruction
)
33 self
.test_in1(pdecode2
, pdecode
)
35 self
.test_in2_fields()
39 self
.test_single_bits()
43 def test_in1(self
, pdecode2
, pdecode
):
46 ra
= self
.instr_bits(11, 15)
47 with m
.If(pdecode
.op
.in1_sel
== In1Sel
.RA
):
48 comb
+= Assert(pdecode2
.e
.read_reg1
.data
== ra
)
49 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 1)
50 with m
.If(pdecode
.op
.in1_sel
== In1Sel
.RA_OR_ZERO
):
52 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 0)
54 comb
+= Assert(pdecode2
.e
.read_reg1
.data
== ra
)
55 comb
+= Assert(pdecode2
.e
.read_reg1
.ok
== 1)
56 op
= pdecode
.op
.internal_op
57 with m
.If((op
== MicrOp
.OP_BC
) |
58 (op
== MicrOp
.OP_BCREG
)):
59 with m
.If(~self
.instr_bits(8)):
60 comb
+= Assert(pdecode2
.e
.read_spr1
.data
== SPR
.CTR
)
61 comb
+= Assert(pdecode2
.e
.read_spr1
.ok
== 1)
62 with m
.If((op
== MicrOp
.OP_MFSPR
) |
63 (op
== MicrOp
.OP_MTSPR
)):
64 comb
+= Assert(pdecode2
.e
.read_spr1
.data
==
65 self
.instr_bits(11, 20))
66 comb
+= Assert(pdecode2
.e
.read_spr1
.ok
== 1)
71 pdecode2
= m
.submodules
.pdecode2
73 with m
.If(dec
.op
.in2_sel
== In2Sel
.RB
):
74 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 1)
75 comb
+= Assert(pdecode2
.e
.read_reg2
.data
== dec
.RB
)
76 with m
.Elif(dec
.op
.in2_sel
== In2Sel
.NONE
):
77 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 0)
78 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 0)
79 with m
.Elif(dec
.op
.in2_sel
== In2Sel
.SPR
):
80 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 0)
81 comb
+= Assert(pdecode2
.e
.read_reg2
.ok
== 0)
82 comb
+= Assert(pdecode2
.e
.read_spr2
.ok
== 1)
83 with m
.If(dec
.fields
.FormXL
.XO
[9]):
84 comb
+= Assert(pdecode2
.e
.read_spr2
.data
== SPR
.CTR
)
86 comb
+= Assert(pdecode2
.e
.read_spr2
.data
== SPR
.LR
)
88 comb
+= Assert(pdecode2
.e
.imm_data
.ok
== 1)
89 with m
.Switch(dec
.op
.in2_sel
):
90 with m
.Case(In2Sel
.CONST_UI
):
91 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.UI
)
92 with m
.Case(In2Sel
.CONST_SI
):
93 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
94 self
.exts(dec
.SI
, 16, 64))
95 with m
.Case(In2Sel
.CONST_UI_HI
):
96 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.UI
<< 16))
97 with m
.Case(In2Sel
.CONST_SI_HI
):
98 comb
+= Assert(pdecode2
.e
.imm_data
.data
==
99 self
.exts(dec
.SI
<< 16, 32, 64))
100 with m
.Case(In2Sel
.CONST_LI
):
101 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.LI
<< 2))
102 with m
.Case(In2Sel
.CONST_BD
):
103 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.BD
<< 2))
104 with m
.Case(In2Sel
.CONST_DS
):
105 comb
+= Assert(pdecode2
.e
.imm_data
.data
== (dec
.DS
<< 2))
106 with m
.Case(In2Sel
.CONST_M1
):
107 comb
+= Assert(pdecode2
.e
.imm_data
.data
== ~
0)
108 with m
.Case(In2Sel
.CONST_SH
):
109 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.sh
)
110 with m
.Case(In2Sel
.CONST_SH32
):
111 comb
+= Assert(pdecode2
.e
.imm_data
.data
== dec
.SH32
)
115 def exts(self
, exts_data
, width
, fullwidth
):
116 exts_data
= exts_data
[0:width
]
117 topbit
= exts_data
[-1]
118 signbits
= Repl(topbit
, fullwidth
-width
)
119 return Cat(exts_data
, signbits
)
121 def test_in2_fields(self
):
124 dec
= m
.submodules
.pdecode2
.dec
126 comb
+= Assert(dec
.RB
== self
.instr_bits(16, 20))
127 comb
+= Assert(dec
.UI
== self
.instr_bits(16, 31))
128 comb
+= Assert(dec
.SI
== self
.instr_bits(16, 31))
129 comb
+= Assert(dec
.LI
== self
.instr_bits(6, 29))
130 comb
+= Assert(dec
.BD
== self
.instr_bits(16, 29))
131 comb
+= Assert(dec
.DS
== self
.instr_bits(16, 29))
132 comb
+= Assert(dec
.sh
== Cat(self
.instr_bits(16, 20),
133 self
.instr_bits(30)))
134 comb
+= Assert(dec
.SH32
== self
.instr_bits(16, 20))
139 pdecode2
= m
.submodules
.pdecode2
140 with m
.If(pdecode2
.dec
.op
.in3_sel
== In3Sel
.RS
):
141 comb
+= Assert(pdecode2
.e
.read_reg3
.ok
== 1)
142 comb
+= Assert(pdecode2
.e
.read_reg3
.data
== self
.instr_bits(6, 10))
147 pdecode2
= m
.submodules
.pdecode2
148 sel
= pdecode2
.dec
.op
.out_sel
150 with m
.If(sel
== OutSel
.SPR
):
151 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 1)
152 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 0)
153 with m
.Elif(sel
== OutSel
.NONE
):
154 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 0)
155 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 0)
157 comb
+= Assert(pdecode2
.e
.write_spr
.ok
== 0)
158 comb
+= Assert(pdecode2
.e
.write_reg
.ok
== 1)
159 data
= pdecode2
.e
.write_reg
.data
160 with m
.If(sel
== OutSel
.RT
):
161 comb
+= Assert(data
== self
.instr_bits(6, 10))
162 with m
.If(sel
== OutSel
.RA
):
163 comb
+= Assert(data
== self
.instr_bits(11, 15))
168 pdecode2
= m
.submodules
.pdecode2
169 sel
= pdecode2
.dec
.op
.rc_sel
171 comb
+= Assert(pdecode2
.e
.rc
.ok
== 1)
172 # no RC: rc.data must be zero
173 with m
.If(sel
== RCOE
.NONE
):
174 comb
+= Assert(pdecode2
.e
.rc
.data
== 0)
175 # RC permanently set: rc.data must be hard-coded to 1
176 with m
.If(sel
== RCOE
.ONE
):
177 comb
+= Assert(pdecode2
.e
.rc
.data
== 1)
178 # RCOE.RC covers both RC and OE
179 with m
.If(sel
== RCOE
.RC
):
180 comb
+= Assert(pdecode2
.e
.rc
.data
== dec
.Rc
)
181 comb
+= Assert(pdecode2
.e
.oe
.ok
== 1)
182 comb
+= Assert(pdecode2
.e
.oe
.data
== dec
.OE
)
183 # RCOE.RC_ONLY covers just RC: OE remains zero.
184 with m
.If(sel
== RCOE
.RC_ONLY
):
185 comb
+= Assert(pdecode2
.e
.rc
.data
== dec
.Rc
)
186 comb
+= Assert(pdecode2
.e
.oe
.ok
== 0)
188 def test_single_bits(self
):
191 pdecode2
= m
.submodules
.pdecode2
194 comb
+= Assert(e
.invert_in
== dec
.op
.inv_a
)
195 comb
+= Assert(e
.invert_out
== dec
.op
.inv_out
)
196 comb
+= Assert(e
.input_carry
== dec
.op
.cry_in
)
197 comb
+= Assert(e
.output_carry
== dec
.op
.cry_out
)
198 comb
+= Assert(e
.is_32bit
== dec
.op
.is_32b
)
199 comb
+= Assert(e
.is_signed
== dec
.op
.sgn
)
200 with m
.If(dec
.op
.lk
):
201 comb
+= Assert(e
.lk
== self
.instr_bits(31))
202 comb
+= Assert(e
.byte_reverse
== dec
.op
.br
)
203 comb
+= Assert(e
.sign_extend
== dec
.op
.sgn_ext
)
204 comb
+= Assert(e
.update
== dec
.op
.upd
)
205 comb
+= Assert(e
.input_cr
== dec
.op
.cr_in
)
206 comb
+= Assert(e
.output_cr
== dec
.op
.cr_out
)
208 def instr_bits(self
, start
, end
=None):
211 return self
.instruction
[::-1][start
:end
+1][::-1]
214 class Decoder2TestCase(FHDLTestCase
):
215 @unittest.expectedFailure
# FIXME: `pdecode2.e.imm_data` AttributeError
216 def test_decoder2(self
):
218 self
.assertFormal(module
, mode
="bmc", depth
=4)
221 if __name__
== '__main__':