src/openpower/decoder/isa/test_caller_ldst_exceptions.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, inject
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.consts import PIb
  14
  15
  16 class Register:
  17     def __init__(self, num):
  18         self.num = num
  19
  20 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
  21                                      initial_cr=0,mem=None):
  22     if initial_sprs is None:
  23         initial_sprs = {}
  24     m = Module()
  25     comb = m.d.comb
  26     instruction = Signal(32)
  27
  28     pdecode = create_pdecode()
  29
  30     gen = list(generator.generate_instructions())
  31     insncode = generator.assembly.splitlines()
  32     instructions = list(zip(gen, insncode))
  33
  34     m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  35     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
  36                     initial_insns=gen, respect_pc=True,
  37                     initial_svstate=svstate,
  38                     initial_mem=mem,
  39                     disassembly=insncode,
  40                     bigendian=0,
  41                     mmu=mmu)
  42     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  43     sim = Simulator(m)
  44
  45
  46     def process():
  47
  48         yield pdecode2.dec.bigendian.eq(0)  # little / big?
  49         pc = simulator.pc.CIA.value
  50         index = pc//4
  51         while index < len(instructions):
  52             print("instr pc", pc)
  53             try:
  54                 yield from simulator.setup_one()
  55             except KeyError:  # indicates instruction not in imem: stop
  56                 break
  57             yield Settle()
  58
  59             ins, code = instructions[index]
  60             print("    0x{:X}".format(ins & 0xffffffff))
  61             opname = code.split(' ')[0]
  62             print(code, opname)
  63
  64             # ask the decoder to decode this binary data (endian'd)
  65             yield from simulator.execute_one()
  66             pc = simulator.pc.CIA.value
  67             index = pc//4
  68
  69     sim.add_process(process)
  70     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  71                        traces=[]):
  72         sim.run()
  73     return simulator
  74
  75
  76 class DecoderTestCase(FHDLTestCase):
  77
  78     def test_load_misalign(self):
  79         lst = ["addi 2, 0, 0x0010", # get PC off of zero
  80                "ldx 3, 0, 1",
  81                ]
  82         initial_regs = [0] * 32
  83         all1s = 0xFFFFFFFFFFFFFFFF
  84         initial_regs[1] = all1s
  85         initial_regs[2] = 0x0008
  86         initial_mem = {0x0000: (0x5432123412345678, 8),
  87                        0x0008: (0xabcdef0187654321, 8),
  88                        0x0020: (0x1828384822324252, 8),
  89                         }
  90
  91         with Program(lst, bigendian=False) as program:
  92             sim = self.run_tst_program(program, initial_regs, initial_mem)
  93             self.assertEqual(sim.gpr(1), SelectableInt(all1s, 64))
  94             self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
  95             print ("DAR", hex(sim.spr['DAR'].value))
  96             print ("PC", hex(sim.pc.CIA.value))
  97             # TODO get MSR, test that.
  98             # TODO, test rest of SRR1 equal to zero
  99             self.assertEqual(sim.spr['SRR1'][PIb.PRIV], 0x1) # expect priv bit
 100             self.assertEqual(sim.spr['SRR0'], 0x4)   # expect to be 2nd op
 101             self.assertEqual(sim.spr['DAR'], all1s)   # expect failed LD addr
 102             self.assertEqual(sim.pc.CIA.value, 0x600) # align exception
 103
 104     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None):
 105         simulator = run_tst(prog, initial_regs, mem=initial_mem)
 106         simulator.gpr.dump()
 107         return simulator
 108
 109
 110 if __name__ == "__main__":
 111     unittest.main()