src/openpower/decoder/isa/test_caller_ldst_exceptions.py

   1 import unittest
   2
   3 from nmigen import Module, Signal
   4 from nmigen.sim import Settle, Simulator
   5 from nmutil.formaltest import FHDLTestCase
   6 from openpower.consts import PIb
   7 from openpower.decoder.isa.all import ISA
   8 from openpower.decoder.power_decoder import create_pdecode
   9 from openpower.decoder.power_decoder2 import PowerDecode2
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.simulator.program import Program
  12
  13
  14 class Register:
  15     def __init__(self, num):
  16         self.num = num
  17
  18
  19 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
  20             initial_cr=0, mem=None):
  21     if initial_sprs is None:
  22         initial_sprs = {}
  23     m = Module()
  24     comb = m.d.comb
  25     instruction = Signal(32)
  26
  27     pdecode = create_pdecode()
  28
  29     gen = list(generator.generate_instructions())
  30     insncode = generator.assembly.splitlines()
  31     instructions = list(zip(gen, insncode))
  32
  33     m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  34     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
  35                     initial_insns=gen, respect_pc=True,
  36                     initial_svstate=svstate,
  37                     initial_mem=mem,
  38                     disassembly=insncode,
  39                     bigendian=0,
  40                     mmu=mmu)
  41     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  42     sim = Simulator(m)
  43
  44     def process():
  45
  46         yield pdecode2.dec.bigendian.eq(0)  # little / big?
  47         pc = simulator.pc.CIA.value
  48         index = pc//4
  49         while index < len(instructions):
  50             print("instr pc", pc)
  51             try:
  52                 yield from simulator.setup_one()
  53             except KeyError:  # indicates instruction not in imem: stop
  54                 break
  55             yield Settle()
  56
  57             ins, code = instructions[index]
  58             print("    0x{:X}".format(ins & 0xffffffff))
  59             opname = code.split(' ')[0]
  60             print(code, opname)
  61
  62             # ask the decoder to decode this binary data (endian'd)
  63             yield from simulator.execute_one()
  64             pc = simulator.pc.CIA.value
  65             index = pc//4
  66
  67     sim.add_process(process)
  68     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  69                        traces=[]):
  70         sim.run()
  71     return simulator
  72
  73
  74 class DecoderTestCase(FHDLTestCase):
  75
  76     def test_load_misalign(self):
  77         lst = ["addi 2, 0, 0x0010",  # get PC off of zero
  78                "ldx 3, 0, 1",
  79                ]
  80         initial_regs = [0] * 32
  81         all1s = 0xFFFFFFFFFFFFFFFF
  82         initial_regs[1] = all1s
  83         initial_regs[2] = 0x0008
  84         initial_mem = {0x0000: (0x5432123412345678, 8),
  85                        0x0008: (0xabcdef0187654321, 8),
  86                        0x0020: (0x1828384822324252, 8),
  87                        }
  88
  89         with Program(lst, bigendian=False) as program:
  90             sim = self.run_tst_program(program, initial_regs, initial_mem)
  91             self.assertEqual(sim.gpr(1), SelectableInt(all1s, 64))
  92             self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
  93             print("DAR", hex(sim.spr['DAR'].value))
  94             print("PC", hex(sim.pc.CIA.value))
  95             # TODO get MSR, test that.
  96             # TODO, test rest of SRR1 equal to zero
  97             self.assertEqual(sim.spr['SRR1'][PIb.PRIV], 0x1)  # expect priv bit
  98             self.assertEqual(sim.spr['SRR0'], 0x4)   # expect to be 2nd op
  99             self.assertEqual(sim.spr['DAR'], all1s)   # expect failed LD addr
 100             self.assertEqual(sim.pc.CIA.value, 0x600)  # align exception
 101
 102     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None):
 103         simulator = run_tst(prog, initial_regs, mem=initial_mem)
 104         simulator.gpr.dump()
 105         return simulator
 106
 107
 108 if __name__ == "__main__":
 109     unittest.main()