1 from nmigen
import Module
, Signal
2 #from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, inject
, RADIX
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import run_tst
15 from copy
import deepcopy
19 0x10000: # PARTITION_TABLE_2 (not implemented yet)
20 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
23 0x30000: # RADIX_ROOT_PTE
24 # V = 1 L = 0 NLB = 0x400 NLS = 9
26 0x40000: # RADIX_SECOND_LEVEL
27 # V = 1 L = 1 SW = 0 RPN = 0
28 # R = 1 C = 1 ATT = 0 EAA 0x7
31 0x30800: # RADIX_ROOT_PTE + 8
32 # V = 1 L = 0 NLB = 0x408 NLS = 9
34 0x40800: # RADIX_SECOND_LEVEL
35 # V = 1 L = 1 SW = 0 RPN = 0
36 # R = 1 C = 1 ATT = 0 EAA 0x7
39 0x1000000: # PROCESS_TABLE_3
40 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
42 0x1000008: # PROCESS_TABLE_3 + 8
43 # RTS1 = 0x2 RPDB = 0x308 RTS2 = 0x5 RPDS = 13
47 prtbl
= 0x1000000 # matches PROCESS_TABLE_3 above
49 class DecoderTestCase(FHDLTestCase
):
54 sprs
= {'DSISR': SelectableInt(0, 64),
55 'DAR': SelectableInt(0, 64),
56 'PIDR': SelectableInt(0, 64),
57 'PRTBL': SelectableInt(prtbl
, 64)
61 initial_regs
[1] = 0x1000
62 initial_regs
[2] = 0x1234
64 initial_mem
= deepcopy(testmem
)
65 initial_mem
[0x1000] = 0x1337 # data to be read
67 with
Program(lst
, bigendian
=False) as program
:
68 sim
= self
.run_tst_program(program
, initial_regs
=initial_regs
,
69 initial_mem
=initial_mem
,
71 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1337, 64))
73 def test_load_pid_1(self
):
76 sprs
= {'DSISR': SelectableInt(0, 64),
77 'DAR': SelectableInt(0, 64),
78 'PIDR': SelectableInt(1, 64),
79 'PRTBL': SelectableInt(prtbl
, 64)
83 initial_regs
[1] = 0x1000
84 initial_regs
[2] = 0x1234
86 initial_mem
= deepcopy(testmem
)
87 initial_mem
[0x1000] = 0x1337 # data to be read
89 with
Program(lst
, bigendian
=False) as program
:
90 sim
= self
.run_tst_program(program
, initial_regs
=initial_regs
,
91 initial_mem
=initial_mem
,
93 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1337, 64))
95 def test_load_store(self
):
96 lst
= ["addi 1, 0, 0x1000",
101 # set up dummy minimal ISACaller
102 sprs
= {'DSISR': SelectableInt(0, 64),
103 'DAR': SelectableInt(0, 64),
104 'PIDR': SelectableInt(0, 64),
105 'PRTBL': SelectableInt(prtbl
, 64)
108 initial_regs
=[0] * 32
109 initial_regs
[1] = 0x1000
110 initial_regs
[2] = 0x1234
111 initial_mem
= deepcopy(testmem
)
113 with
Program(lst
, bigendian
=False) as program
:
114 sim
= self
.run_tst_program(program
, initial_regs
=initial_regs
,
115 initial_mem
=initial_mem
,
117 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1234, 64))
119 def run_tst_program(self
, prog
, initial_regs
=None, initial_mem
=None,
121 # DO NOT set complex arguments, it is a "singleton" pattern
122 if initial_regs
is None:
123 initial_regs
= [0] * 32
125 simulator
= run_tst(prog
, initial_regs
, mmu
=True, mem
=initial_mem
,
126 initial_sprs
=initial_sprs
)
131 if __name__
== "__main__":