src/openpower/decoder/isa/test_caller_setvl.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_setvl_1(self):
  25         lst = SVP64Asm(["setvl 1, 0, 9, 1, 1",
  26                         ])
  27         lst = list(lst)
  28
  29         # SVSTATE (in this case, VL=2)
  30         svstate = SVP64State()
  31         svstate.vl[0:7] = 2 # VL
  32         svstate.maxvl[0:7] = 2 # MAXVL
  33         print ("SVSTATE", bin(svstate.spr.asint()))
  34
  35         with Program(lst, bigendian=False) as program:
  36             sim = self.run_tst_program(program, svstate=svstate)
  37             print ("SVSTATE after", bin(sim.svstate.spr.asint()))
  38             print ("        vl", bin(sim.svstate.vl.asint(True)))
  39             print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
  40             self.assertEqual(sim.svstate.vl.asint(True), 10)
  41             self.assertEqual(sim.svstate.maxvl.asint(True), 10)
  42             self.assertEqual(sim.svstate.maxvl.asint(True), 10)
  43             print("      gpr1", sim.gpr(1))
  44             self.assertEqual(sim.gpr(1), SelectableInt(10, 64))
  45
  46
  47     def test_sv_add(self):
  48         # sets VL=2 then adds:
  49         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  50         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  51         isa = SVP64Asm(["setvl 3, 0, 1, 1, 1",
  52                         'sv.add 1.v, 5.v, 9.v'
  53                        ])
  54         lst = list(isa)
  55         print ("listing", lst)
  56
  57         # initial values in GPR regfile
  58         initial_regs = [0] * 32
  59         initial_regs[9] = 0x1234
  60         initial_regs[10] = 0x1111
  61         initial_regs[5] = 0x4321
  62         initial_regs[6] = 0x2223
  63
  64         # copy before running
  65         expected_regs = deepcopy(initial_regs)
  66         expected_regs[1] = 0x5555
  67         expected_regs[2] = 0x3334
  68         expected_regs[3] = 2       # setvl places copy of VL here
  69
  70         with Program(lst, bigendian=False) as program:
  71             sim = self.run_tst_program(program, initial_regs)
  72             self._check_regs(sim, expected_regs)
  73
  74     def run_tst_program(self, prog, initial_regs=None,
  75                               svstate=None):
  76         if initial_regs is None:
  77             initial_regs = [0] * 32
  78         simulator = run_tst(prog, initial_regs, svstate=svstate)
  79         simulator.gpr.dump()
  80         return simulator
  81
  82
  83 if __name__ == "__main__":
  84     unittest.main()
  85