src/openpower/decoder/isa/test_caller_setvl.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         print ("GPR")
  22         sim.gpr.dump()
  23         for i in range(32):
  24             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  25
  26     def test_1_setvl_zero_rc1(self):
  27         lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1",
  28                         ])
  29         lst = list(lst)
  30
  31         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
  32         # but, ha! r4 (RA) is zero. and Rc=1. therefore, CR0 should be set EQ
  33         svstate = SVP64State()
  34         svstate.maxvl = 5 # MAXVL
  35         print ("SVSTATE", bin(svstate.asint()))
  36
  37         with Program(lst, bigendian=False) as program:
  38             sim = self.run_tst_program(program, svstate=svstate)
  39             print ("SVSTATE after", bin(sim.svstate.asint()))
  40             print ("        vl", bin(sim.svstate.vl))
  41             print ("        mvl", bin(sim.svstate.maxvl))
  42             print ("    srcstep", bin(sim.svstate.srcstep))
  43             print ("    dststep", bin(sim.svstate.dststep))
  44             print ("     vfirst", bin(sim.svstate.vfirst))
  45             self.assertEqual(sim.svstate.vl, 0)
  46             self.assertEqual(sim.svstate.maxvl, 5)
  47             self.assertEqual(sim.svstate.srcstep, 0)
  48             self.assertEqual(sim.svstate.dststep, 0)
  49             self.assertEqual(sim.svstate.vfirst, 0)
  50             print("      gpr4", sim.gpr(4))
  51             self.assertEqual(sim.gpr(4), SelectableInt(0, 64))
  52             print("      gpr5", sim.gpr(5))
  53             self.assertEqual(sim.gpr(5), SelectableInt(0, 64))
  54             CR0 = sim.crl[0]
  55             print("      CR0", bin(CR0.get_range().value))
  56             self.assertEqual(CR0[CRFields.EQ], 1)
  57             self.assertEqual(CR0[CRFields.LT], 0)
  58             self.assertEqual(CR0[CRFields.GT], 0)
  59             self.assertEqual(CR0[CRFields.SO], 0)
  60
  61     def test_2_setvl_nonzero_rc1(self):
  62         lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1",
  63                         ])
  64         lst = list(lst)
  65
  66         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
  67         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
  68         svstate = SVP64State()
  69         svstate.maxvl = 5 # MAXVL
  70         print ("SVSTATE", bin(svstate.asint()))
  71
  72         initial_regs = [0] * 32
  73         initial_regs[4] = 4
  74
  75         with Program(lst, bigendian=False) as program:
  76             sim = self.run_tst_program(program, svstate=svstate,
  77                                        initial_regs=initial_regs)
  78             print ("SVSTATE after", bin(sim.svstate.asint()))
  79             print ("        vl", bin(sim.svstate.vl))
  80             print ("        mvl", bin(sim.svstate.maxvl))
  81             print ("    srcstep", bin(sim.svstate.srcstep))
  82             print ("    dststep", bin(sim.svstate.dststep))
  83             print ("     vfirst", bin(sim.svstate.vfirst))
  84             self.assertEqual(sim.svstate.vl, 4)
  85             self.assertEqual(sim.svstate.maxvl, 5)
  86             self.assertEqual(sim.svstate.srcstep, 0)
  87             self.assertEqual(sim.svstate.dststep, 0)
  88             self.assertEqual(sim.svstate.vfirst, 0)
  89             print("      gpr4", sim.gpr(4))
  90             self.assertEqual(sim.gpr(4), SelectableInt(4, 64))
  91             print("      gpr5", sim.gpr(5))
  92             self.assertEqual(sim.gpr(5), SelectableInt(4, 64))
  93             CR0 = sim.crl[0]
  94             print("      CR0", bin(CR0.get_range().value))
  95             self.assertEqual(CR0[CRFields.EQ], 0)
  96             self.assertEqual(CR0[CRFields.LT], 0)
  97             self.assertEqual(CR0[CRFields.GT], 1)
  98             self.assertEqual(CR0[CRFields.SO], 0)
  99
 100     def test_3_setvl_overflow_rc1(self):
 101         lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1",
 102                         ])
 103         lst = list(lst)
 104
 105         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 106         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 107         svstate = SVP64State()
 108         svstate.maxvl = 5 # MAXVL
 109         print ("SVSTATE", bin(svstate.asint()))
 110
 111         initial_regs = [0] * 32
 112         initial_regs[4] = 1000 # much greater than MAXVL
 113
 114         with Program(lst, bigendian=False) as program:
 115             sim = self.run_tst_program(program, svstate=svstate,
 116                                        initial_regs=initial_regs)
 117             print ("SVSTATE after", bin(sim.svstate.asint()))
 118             print ("        vl", bin(sim.svstate.vl))
 119             print ("        mvl", bin(sim.svstate.maxvl))
 120             print ("    srcstep", bin(sim.svstate.srcstep))
 121             print ("    dststep", bin(sim.svstate.dststep))
 122             print ("     vfirst", bin(sim.svstate.vfirst))
 123             self.assertEqual(sim.svstate.vl, 5)
 124             self.assertEqual(sim.svstate.maxvl, 5)
 125             self.assertEqual(sim.svstate.srcstep, 0)
 126             self.assertEqual(sim.svstate.dststep, 0)
 127             self.assertEqual(sim.svstate.vfirst, 0)
 128             print("      gpr4", sim.gpr(4))
 129             self.assertEqual(sim.gpr(4), SelectableInt(1000, 64)) # unmodified
 130             print("      gpr5", sim.gpr(5))
 131             self.assertEqual(sim.gpr(5), SelectableInt(5, 64)) # equal to MAXVL
 132             CR0 = sim.crl[0]
 133             print("      CR0", bin(CR0.get_range().value))
 134             self.assertEqual(CR0[CRFields.EQ], 0)
 135             self.assertEqual(CR0[CRFields.LT], 0)
 136             self.assertEqual(CR0[CRFields.GT], 1)
 137             self.assertEqual(CR0[CRFields.SO], 1)
 138
 139     def test_4_setvl_max_overflow_rc1(self):
 140         """this should set overflow even though VL gets set to MAXVL
 141         at its limit of 127 (0b1111111)
 142         """
 143         lst = SVP64Asm(["setvl. 5, 4, 127, 0, 1, 1",
 144                         ])
 145         lst = list(lst)
 146
 147         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 148         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 149         svstate = SVP64State()
 150         svstate.maxvl = 5 # MAXVL
 151         print ("SVSTATE", bin(svstate.asint()))
 152
 153         initial_regs = [0] * 32
 154         initial_regs[4] = 1000 # much greater than MAXVL
 155
 156         with Program(lst, bigendian=False) as program:
 157             sim = self.run_tst_program(program, svstate=svstate,
 158                                        initial_regs=initial_regs)
 159             print ("SVSTATE after", bin(sim.svstate.asint()))
 160             print ("        vl", bin(sim.svstate.vl))
 161             print ("        mvl", bin(sim.svstate.maxvl))
 162             print ("    srcstep", bin(sim.svstate.srcstep))
 163             print ("    dststep", bin(sim.svstate.dststep))
 164             print ("     vfirst", bin(sim.svstate.vfirst))
 165             self.assertEqual(sim.svstate.vl, 127)
 166             self.assertEqual(sim.svstate.maxvl, 127)
 167             self.assertEqual(sim.svstate.srcstep, 0)
 168             self.assertEqual(sim.svstate.dststep, 0)
 169             self.assertEqual(sim.svstate.vfirst, 0)
 170             print("      gpr4", sim.gpr(4))
 171             self.assertEqual(sim.gpr(4), SelectableInt(1000, 64)) # unmodified
 172             print("      gpr5", sim.gpr(5))
 173             self.assertEqual(sim.gpr(5), SelectableInt(127, 64)) # eq. MAXVL
 174             CR0 = sim.crl[0]
 175             print("      CR0", bin(CR0.get_range().value))
 176             self.assertEqual(CR0[CRFields.EQ], 0)
 177             self.assertEqual(CR0[CRFields.LT], 0)
 178             self.assertEqual(CR0[CRFields.GT], 1)
 179             self.assertEqual(CR0[CRFields.SO], 1)
 180
 181     def test_5_setvl_max_rc1(self):
 182         """this should not set when VL gets set to MAXVL
 183         at its limit of 127 (0b1111111)
 184         """
 185         lst = SVP64Asm(["setvl. 5, 4, 127, 0, 1, 1",
 186                         ])
 187         lst = list(lst)
 188
 189         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 190         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 191         svstate = SVP64State()
 192         svstate.maxvl = 5 # MAXVL
 193         print ("SVSTATE", bin(svstate.asint()))
 194
 195         initial_regs = [0] * 32
 196         initial_regs[4] = 127 # exactly equal to MAXVL
 197
 198         with Program(lst, bigendian=False) as program:
 199             sim = self.run_tst_program(program, svstate=svstate,
 200                                        initial_regs=initial_regs)
 201             print ("SVSTATE after", bin(sim.svstate.asint()))
 202             print ("        vl", bin(sim.svstate.vl))
 203             print ("        mvl", bin(sim.svstate.maxvl))
 204             print ("    srcstep", bin(sim.svstate.srcstep))
 205             print ("    dststep", bin(sim.svstate.dststep))
 206             print ("     vfirst", bin(sim.svstate.vfirst))
 207             self.assertEqual(sim.svstate.vl, 127)
 208             self.assertEqual(sim.svstate.maxvl, 127)
 209             self.assertEqual(sim.svstate.srcstep, 0)
 210             self.assertEqual(sim.svstate.dststep, 0)
 211             self.assertEqual(sim.svstate.vfirst, 0)
 212             print("      gpr4", sim.gpr(4))
 213             self.assertEqual(sim.gpr(4), SelectableInt(127, 64)) # unmodified
 214             print("      gpr5", sim.gpr(5))
 215             self.assertEqual(sim.gpr(5), SelectableInt(127, 64)) # eq. MAXVL
 216             CR0 = sim.crl[0]
 217             print("      CR0", bin(CR0.get_range().value))
 218             self.assertEqual(CR0[CRFields.EQ], 0)
 219             self.assertEqual(CR0[CRFields.LT], 0)
 220             self.assertEqual(CR0[CRFields.GT], 1)
 221             self.assertEqual(CR0[CRFields.SO], 0)
 222
 223     def test_5_setvl_rt0_rc1(self):
 224         """odd one. Rc=1, RT=0, RA!=0, so RT does not get set, but VL does.
 225         confirms that when Rc=1 and RT is unmodified that CR0 still is updated
 226         """
 227         lst = SVP64Asm(["setvl. 0, 4, 5, 0, 1, 1",
 228                         ])
 229         lst = list(lst)
 230
 231         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 232         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 233         svstate = SVP64State()
 234         svstate.maxvl = 5 # MAXVL
 235         print ("SVSTATE", bin(svstate.asint()))
 236
 237         initial_regs = [0] * 32
 238         initial_regs[4] = 127 # overlimit, should set CR0.SO=1, and CR0.GT=1
 239
 240         with Program(lst, bigendian=False) as program:
 241             sim = self.run_tst_program(program, svstate=svstate,
 242                                        initial_regs=initial_regs)
 243             print ("SVSTATE after", bin(sim.svstate.asint()))
 244             print ("        vl", bin(sim.svstate.vl))
 245             print ("        mvl", bin(sim.svstate.maxvl))
 246             print ("    srcstep", bin(sim.svstate.srcstep))
 247             print ("    dststep", bin(sim.svstate.dststep))
 248             print ("     vfirst", bin(sim.svstate.vfirst))
 249             self.assertEqual(sim.svstate.vl, 5)
 250             self.assertEqual(sim.svstate.maxvl, 5)
 251             self.assertEqual(sim.svstate.srcstep, 0)
 252             self.assertEqual(sim.svstate.dststep, 0)
 253             self.assertEqual(sim.svstate.vfirst, 0)
 254             print("      gpr0", sim.gpr(0))
 255             self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) # unmodified
 256             print("      gpr4", sim.gpr(4))
 257             self.assertEqual(sim.gpr(4), SelectableInt(127, 64)) # unmodified
 258             CR0 = sim.crl[0]
 259             print("      CR0", bin(CR0.get_range().value))
 260             self.assertEqual(CR0[CRFields.EQ], 0)
 261             self.assertEqual(CR0[CRFields.LT], 0)
 262             self.assertEqual(CR0[CRFields.GT], 1)
 263             self.assertEqual(CR0[CRFields.SO], 1)
 264
 265     def test_svstep_1(self):
 266         lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode)
 267                         "setvl 0, 0, 1, 1, 0, 0", # svstep
 268                         "setvl 0, 0, 1, 1, 0, 0" # svstep
 269                         ])
 270         lst = list(lst)
 271
 272         # SVSTATE (in this case, VL=4) which is going to get erased by setvl
 273         svstate = SVP64State()
 274         svstate.vl = 4 # VL
 275         svstate.maxvl = 4 # MAXVL
 276         print ("SVSTATE", bin(svstate.asint()))
 277
 278         with Program(lst, bigendian=False) as program:
 279             sim = self.run_tst_program(program, svstate=svstate)
 280             print ("SVSTATE after", bin(sim.svstate.asint()))
 281             print ("        vl", bin(sim.svstate.vl))
 282             print ("        mvl", bin(sim.svstate.maxvl))
 283             print ("    srcstep", bin(sim.svstate.srcstep))
 284             print ("    dststep", bin(sim.svstate.dststep))
 285             print ("     vfirst", bin(sim.svstate.vfirst))
 286             self.assertEqual(sim.svstate.vl, 10)
 287             self.assertEqual(sim.svstate.maxvl, 10)
 288             self.assertEqual(sim.svstate.srcstep, 2)
 289             self.assertEqual(sim.svstate.dststep, 2)
 290             self.assertEqual(sim.svstate.vfirst, 1)
 291             print("      gpr1", sim.gpr(0))
 292             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 293
 294     def test_svstep_2(self):
 295         """tests svstep when it reaches VL
 296         """
 297         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",  # actual setvl (VF mode)
 298                         "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
 299                         "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
 300                         ])
 301         lst = list(lst)
 302
 303         # SVSTATE (in this case, VL=2)
 304         svstate = SVP64State()
 305         svstate.vl = 2 # VL
 306         svstate.maxvl = 2 # MAXVL
 307         print ("SVSTATE", bin(svstate.asint()))
 308
 309         with Program(lst, bigendian=False) as program:
 310             sim = self.run_tst_program(program, svstate=svstate)
 311             print ("SVSTATE after", bin(sim.svstate.asint()))
 312             print ("        vl", bin(sim.svstate.vl))
 313             print ("        mvl", bin(sim.svstate.maxvl))
 314             print ("    srcstep", bin(sim.svstate.srcstep))
 315             print ("    dststep", bin(sim.svstate.dststep))
 316             print ("     vfirst", bin(sim.svstate.vfirst))
 317             self.assertEqual(sim.svstate.vl, 2)
 318             self.assertEqual(sim.svstate.maxvl, 2)
 319             self.assertEqual(sim.svstate.srcstep, 0)
 320             self.assertEqual(sim.svstate.dststep, 0)
 321             # when end reached, vertical mode is exited
 322             self.assertEqual(sim.svstate.vfirst, 0)
 323             print("      gpr1", sim.gpr(0))
 324             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 325             CR0 = sim.crl[0]
 326             print("      CR0", bin(CR0.get_range().value))
 327             self.assertEqual(CR0[CRFields.EQ], 0)
 328             self.assertEqual(CR0[CRFields.LT], 0)
 329             self.assertEqual(CR0[CRFields.GT], 0)
 330             self.assertEqual(CR0[CRFields.SO], 1)
 331
 332     def test_svstep_3(self):
 333         """tests svstep when it *doesn't* reach VL
 334         """
 335         lst = SVP64Asm(["setvl 0, 0, 3, 1, 1, 1",  # actual setvl (VF mode)
 336                         "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
 337                         "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
 338                         ])
 339         lst = list(lst)
 340
 341         # SVSTATE (in this case, VL=2)
 342         svstate = SVP64State()
 343         svstate.vl = 2 # VL
 344         svstate.maxvl = 2 # MAXVL
 345         print ("SVSTATE", bin(svstate.asint()))
 346
 347         with Program(lst, bigendian=False) as program:
 348             sim = self.run_tst_program(program, svstate=svstate)
 349             print ("SVSTATE after", bin(sim.svstate.asint()))
 350             print ("        vl", bin(sim.svstate.vl))
 351             print ("        mvl", bin(sim.svstate.maxvl))
 352             print ("    srcstep", bin(sim.svstate.srcstep))
 353             print ("    dststep", bin(sim.svstate.dststep))
 354             print ("     vfirst", bin(sim.svstate. vfirst))
 355             self.assertEqual(sim.svstate.vl, 3)
 356             self.assertEqual(sim.svstate.maxvl, 3)
 357             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 358             self.assertEqual(sim.svstate.srcstep, 2)
 359             self.assertEqual(sim.svstate.dststep, 2)
 360             print("      gpr1", sim.gpr(0))
 361             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 362             self.assertEqual(sim.svstate.vfirst, 1)
 363             CR0 = sim.crl[0]
 364             print("      CR0", bin(CR0.get_range().value))
 365             self.assertEqual(CR0[CRFields.EQ], 0)
 366             self.assertEqual(CR0[CRFields.LT], 0)
 367             self.assertEqual(CR0[CRFields.GT], 0)
 368             self.assertEqual(CR0[CRFields.SO], 0)
 369
 370     def test_setvl_ctr_1_rc1(self):
 371         """setvl CTR mode, with Rc=1, testing if VL and MVL are over-ridden
 372         and CR0 set correctly
 373         """
 374         lst = SVP64Asm(["setvl. 1, 0, 10, 0, 1, 1",
 375                         ])
 376         lst = list(lst)
 377
 378         # SVSTATE (in this case, VL=2), want to see if these get changed
 379         svstate = SVP64State()
 380         svstate.vl = 2 # VL
 381         svstate.maxvl = 2 # MAXVL
 382         print ("SVSTATE", bin(svstate.asint()))
 383         sprs = {'CTR': 5,
 384                }
 385
 386         with Program(lst, bigendian=False) as program:
 387             sim = self.run_tst_program(program, svstate=svstate,
 388                                        initial_sprs=sprs)
 389             print ("SVSTATE after", bin(sim.svstate.asint()))
 390             print ("        vl", bin(sim.svstate.vl))
 391             print ("        mvl", bin(sim.svstate.maxvl))
 392             self.assertEqual(sim.svstate.vl, 5)
 393             self.assertEqual(sim.svstate.maxvl, 10)
 394             print("      gpr1", sim.gpr(1))
 395             self.assertEqual(sim.gpr(1), SelectableInt(5, 64))
 396
 397             CR0 = sim.crl[0]
 398             print("      CR0", bin(CR0.get_range().value))
 399             self.assertEqual(CR0[CRFields.EQ], 0)
 400             self.assertEqual(CR0[CRFields.LT], 0)
 401             self.assertEqual(CR0[CRFields.GT], 1)
 402             self.assertEqual(CR0[CRFields.SO], 0)
 403
 404     def test_setvl_ctr_1(self):
 405         """setvl CTR mode, testing if VL and MVL are over-ridden
 406         """
 407         lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1",
 408                         ])
 409         lst = list(lst)
 410
 411         # SVSTATE (in this case, VL=2), want to see if these get changed
 412         svstate = SVP64State()
 413         svstate.vl = 2 # VL
 414         svstate.maxvl = 2 # MAXVL
 415         print ("SVSTATE", bin(svstate.asint()))
 416         sprs = {'CTR': 5,
 417                }
 418
 419         with Program(lst, bigendian=False) as program:
 420             sim = self.run_tst_program(program, svstate=svstate,
 421                                        initial_sprs=sprs)
 422             print ("SVSTATE after", bin(sim.svstate.asint()))
 423             print ("        vl", bin(sim.svstate.vl))
 424             print ("        mvl", bin(sim.svstate.maxvl))
 425             self.assertEqual(sim.svstate.vl, 5)
 426             self.assertEqual(sim.svstate.maxvl, 10)
 427             print("      gpr1", sim.gpr(1))
 428             self.assertEqual(sim.gpr(1), SelectableInt(5, 64))
 429
 430             CR0 = sim.crl[0]
 431             print("      CR0", bin(CR0.get_range().value))
 432             self.assertEqual(CR0[CRFields.EQ], 0)
 433             self.assertEqual(CR0[CRFields.LT], 0)
 434             self.assertEqual(CR0[CRFields.GT], 0)
 435             self.assertEqual(CR0[CRFields.SO], 0)
 436
 437     def test_setvl_ctr_2_rc1(self):
 438         """setvl Rc=1, CTR large, testing if VL and MVL are over-ridden,
 439         check if CR0.SO gets set
 440         """
 441         lst = SVP64Asm(["setvl. 1, 0, 10, 0, 1, 1",
 442                         ])
 443         lst = list(lst)
 444
 445         # SVSTATE (in this case, VL=2), want to see if these get changed
 446         svstate = SVP64State()
 447         svstate.vl = 2 # VL
 448         svstate.maxvl = 2 # MAXVL
 449         print ("SVSTATE", bin(svstate.asint()))
 450         sprs = {'CTR': 0x1000000000,
 451                }
 452
 453         with Program(lst, bigendian=False) as program:
 454             sim = self.run_tst_program(program, svstate=svstate,
 455                                        initial_sprs=sprs)
 456             print ("SVSTATE after", bin(sim.svstate.asint()))
 457             print ("        vl", bin(sim.svstate.vl))
 458             print ("        mvl", bin(sim.svstate.maxvl))
 459             self.assertEqual(sim.svstate.vl, 10)
 460             self.assertEqual(sim.svstate.maxvl, 10)
 461             print("      gpr1", sim.gpr(1))
 462             self.assertEqual(sim.gpr(1), SelectableInt(10, 64))
 463
 464             CR0 = sim.crl[0]
 465             print("      CR0", bin(CR0.get_range().value))
 466             self.assertEqual(CR0[CRFields.EQ], 0)
 467             self.assertEqual(CR0[CRFields.LT], 0)
 468             self.assertEqual(CR0[CRFields.GT], 1)
 469             self.assertEqual(CR0[CRFields.SO], 1)
 470
 471     def test_setvl_ctr_2(self):
 472         """setvl CTR large, testing if VL and MVL are over-ridden
 473         """
 474         lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1",
 475                         ])
 476         lst = list(lst)
 477
 478         # SVSTATE (in this case, VL=2), want to see if these get changed
 479         svstate = SVP64State()
 480         svstate.vl = 2 # VL
 481         svstate.maxvl = 2 # MAXVL
 482         print ("SVSTATE", bin(svstate.asint()))
 483         sprs = {'CTR': 0x1000000000,
 484                }
 485
 486         with Program(lst, bigendian=False) as program:
 487             sim = self.run_tst_program(program, svstate=svstate,
 488                                        initial_sprs=sprs)
 489             print ("SVSTATE after", bin(sim.svstate.asint()))
 490             print ("        vl", bin(sim.svstate.vl))
 491             print ("        mvl", bin(sim.svstate.maxvl))
 492             self.assertEqual(sim.svstate.vl, 10)
 493             self.assertEqual(sim.svstate.maxvl, 10)
 494             print("      gpr1", sim.gpr(1))
 495             self.assertEqual(sim.gpr(1), SelectableInt(10, 64))
 496
 497     def test_setvl_1(self):
 498         """straight setvl, testing if VL and MVL are over-ridden
 499         """
 500         lst = SVP64Asm(["setvl 0, 0, 10, 0, 1, 1",
 501                         ])
 502         lst = list(lst)
 503
 504         # SVSTATE (in this case, VL=2), want to see if these get changed
 505         svstate = SVP64State()
 506         svstate.vl = 2 # VL
 507         svstate.maxvl = 2 # MAXVL
 508         print ("SVSTATE", bin(svstate.asint()))
 509
 510         with Program(lst, bigendian=False) as program:
 511             sim = self.run_tst_program(program, svstate=svstate)
 512             print ("SVSTATE after", bin(sim.svstate.asint()))
 513             print ("        vl", bin(sim.svstate.vl))
 514             print ("        mvl", bin(sim.svstate.maxvl))
 515             self.assertEqual(sim.svstate.vl, 10)
 516             self.assertEqual(sim.svstate.maxvl, 10)
 517             print("      gpr1", sim.gpr(1))
 518             self.assertEqual(sim.gpr(1), SelectableInt(0, 64))
 519
 520     def test_setvl_2(self):
 521         """setvl, testing if VL is transferred to RT, and MVL truncates it
 522         """
 523         lst = SVP64Asm(["setvl 1, 0, 2, 0, 0, 1",
 524                         ])
 525         lst = list(lst)
 526
 527         # SVSTATE (in this case, VL=2), want to see if these get changed
 528         svstate = SVP64State()
 529         svstate.vl = 10 # VL
 530         svstate.maxvl = 10 # MAXVL
 531         print ("SVSTATE", bin(svstate.asint()))
 532
 533         with Program(lst, bigendian=False) as program:
 534             sim = self.run_tst_program(program, svstate=svstate)
 535             print ("SVSTATE after", bin(sim.svstate.asint()))
 536             print ("        vl", bin(sim.svstate.vl))
 537             print ("        mvl", bin(sim.svstate.maxvl))
 538             self.assertEqual(sim.svstate.maxvl, 2)
 539             self.assertEqual(sim.svstate.vl, 2)
 540             print("      gpr1", sim.gpr(1))
 541             self.assertEqual(sim.gpr(1), SelectableInt(2, 64))
 542
 543     def test_svstep_inner_loop_6(self):
 544         """tests svstep inner loop, running 6 times, looking for "k".
 545         also sees if k is actually output into reg 2 (RT=2)
 546         """
 547         lst = SVP64Asm([
 548                         # set triple butterfly mode with persistent "REMAP"
 549                         "svshape 8, 1, 1, 1, 1",
 550                         "svremap 31, 1, 0, 2, 0, 1, 1",
 551                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 552                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 553                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 554                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 555                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 556                         "setvl. 2, 0, 2, 1, 0, 0",# svstep (Rc=1)
 557                         ])
 558         lst = list(lst)
 559
 560         # SVSTATE
 561         svstate = SVP64State()
 562         #svstate.vl = 2 # VL
 563         #svstate.maxvl = 2 # MAXVL
 564         print ("SVSTATE", bin(svstate.asint()))
 565
 566         with Program(lst, bigendian=False) as program:
 567             sim = self.run_tst_program(program, svstate=svstate)
 568             print ("SVSTATE after", bin(sim.svstate.asint()))
 569             print ("        vl", bin(sim.svstate.vl))
 570             print ("        mvl", bin(sim.svstate.maxvl))
 571             print ("    srcstep", bin(sim.svstate.srcstep))
 572             print ("    dststep", bin(sim.svstate.dststep))
 573             print ("     vfirst", bin(sim.svstate. vfirst))
 574             self.assertEqual(sim.svstate.vl, 12)
 575             self.assertEqual(sim.svstate.maxvl, 12)
 576             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 577             self.assertEqual(sim.svstate.srcstep, 6)
 578             self.assertEqual(sim.svstate.dststep, 6)
 579             self.assertEqual(sim.gpr(2), SelectableInt(1, 64))
 580             self.assertEqual(sim.svstate.vfirst, 1)
 581             CR0 = sim.crl[0]
 582             print("      CR0", bin(CR0.get_range().value))
 583             self.assertEqual(CR0[CRFields.EQ], 0)
 584             self.assertEqual(CR0[CRFields.LT], 1)
 585             self.assertEqual(CR0[CRFields.GT], 1)
 586             self.assertEqual(CR0[CRFields.SO], 0)
 587
 588     def test_svstep_inner_loop_3(self):
 589         """tests svstep inner loop, running 3 times
 590         """
 591         lst = SVP64Asm([
 592                         # set triple butterfly mode with persistent "REMAP"
 593                         "svshape 8, 1, 1, 1, 1",
 594                         "svremap 31, 1, 0, 2, 0, 1, 1",
 595                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 596                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 597                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 598                         ])
 599         lst = list(lst)
 600
 601         # SVSTATE
 602         svstate = SVP64State()
 603         #svstate.vl = 2 # VL
 604         #svstate.maxvl = 2 # MAXVL
 605         print ("SVSTATE", bin(svstate.asint()))
 606
 607         with Program(lst, bigendian=False) as program:
 608             sim = self.run_tst_program(program, svstate=svstate)
 609             print ("SVSTATE after", bin(sim.svstate.asint()))
 610             print ("        vl", bin(sim.svstate.vl))
 611             print ("        mvl", bin(sim.svstate.maxvl))
 612             print ("    srcstep", bin(sim.svstate.srcstep))
 613             print ("    dststep", bin(sim.svstate.dststep))
 614             print ("     vfirst", bin(sim.svstate. vfirst))
 615             self.assertEqual(sim.svstate.vl, 12)
 616             self.assertEqual(sim.svstate.maxvl, 12)
 617             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 618             self.assertEqual(sim.svstate.srcstep, 3)
 619             self.assertEqual(sim.svstate.dststep, 3)
 620             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 621             self.assertEqual(sim.svstate.vfirst, 1)
 622             CR0 = sim.crl[0]
 623             print("      CR0", bin(CR0.get_range().value))
 624             self.assertEqual(CR0[CRFields.EQ], 0)
 625             self.assertEqual(CR0[CRFields.LT], 1)
 626             self.assertEqual(CR0[CRFields.GT], 1)
 627             self.assertEqual(CR0[CRFields.SO], 0)
 628
 629     def test_svstep_inner_loop_4(self):
 630         """tests svstep inner loop, running 4 times
 631         """
 632         lst = SVP64Asm([
 633                         # set triple butterfly mode with persistent "REMAP"
 634                         "svshape 8, 1, 1, 1, 1",
 635                         "svremap 31, 1, 0, 2, 0, 1, 1",
 636                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 637                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 638                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 639                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 640                         ])
 641         lst = list(lst)
 642
 643         # SVSTATE
 644         svstate = SVP64State()
 645         #svstate.vl = 2 # VL
 646         #svstate.maxvl = 2 # MAXVL
 647         print ("SVSTATE", bin(svstate.asint()))
 648
 649         with Program(lst, bigendian=False) as program:
 650             sim = self.run_tst_program(program, svstate=svstate)
 651             print ("SVSTATE after", bin(sim.svstate.asint()))
 652             print ("        vl", bin(sim.svstate.vl))
 653             print ("        mvl", bin(sim.svstate.maxvl))
 654             print ("    srcstep", bin(sim.svstate.srcstep))
 655             print ("    dststep", bin(sim.svstate.dststep))
 656             print ("     vfirst", bin(sim.svstate. vfirst))
 657             self.assertEqual(sim.svstate.vl, 12)
 658             self.assertEqual(sim.svstate.maxvl, 12)
 659             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 660             self.assertEqual(sim.svstate.srcstep, 4)
 661             self.assertEqual(sim.svstate.dststep, 4)
 662             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 663             self.assertEqual(sim.svstate.vfirst, 1)
 664             CR0 = sim.crl[0]
 665             print("      CR0", bin(CR0.get_range().value))
 666             self.assertEqual(CR0[CRFields.EQ], 0)
 667             self.assertEqual(CR0[CRFields.LT], 1)
 668             self.assertEqual(CR0[CRFields.GT], 0)
 669             self.assertEqual(CR0[CRFields.SO], 0)
 670
 671     def test_svstep_inner_loop_4_jl(self):
 672         """tests svstep inner loop, running 4 times, checking
 673            "jl" is returned after 4th iteration
 674         """
 675         lst = SVP64Asm([
 676                         # set triple butterfly mode with persistent "REMAP"
 677                         "svshape 8, 1, 1, 1, 1",
 678                         "svremap 31, 1, 0, 2, 0, 1, 1",
 679                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 680                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 681                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 682                         "setvl. 2, 0, 2, 1, 0, 0", # svstep (Rc=1)
 683                         ])
 684         lst = list(lst)
 685
 686         # SVSTATE
 687         svstate = SVP64State()
 688         #svstate.vl = 2 # VL
 689         #svstate.maxvl = 2 # MAXVL
 690         print ("SVSTATE", bin(svstate.asint()))
 691
 692         with Program(lst, bigendian=False) as program:
 693             sim = self.run_tst_program(program, svstate=svstate)
 694             print ("SVSTATE after", bin(sim.svstate.asint()))
 695             print ("        vl", bin(sim.svstate.vl))
 696             print ("        mvl", bin(sim.svstate.maxvl))
 697             print ("    srcstep", bin(sim.svstate.srcstep))
 698             print ("    dststep", bin(sim.svstate.dststep))
 699             print ("     vfirst", bin(sim.svstate. vfirst))
 700             self.assertEqual(sim.svstate.vl, 12)
 701             self.assertEqual(sim.svstate.maxvl, 12)
 702             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 703             self.assertEqual(sim.svstate.srcstep, 4)
 704             self.assertEqual(sim.svstate.dststep, 4)
 705             self.assertEqual(sim.gpr(2), SelectableInt(6, 64))
 706             self.assertEqual(sim.svstate.vfirst, 1)
 707             CR0 = sim.crl[0]
 708             print("      CR0", bin(CR0.get_range().value))
 709             self.assertEqual(CR0[CRFields.EQ], 0)
 710             self.assertEqual(CR0[CRFields.LT], 1)
 711             self.assertEqual(CR0[CRFields.GT], 0)
 712             self.assertEqual(CR0[CRFields.SO], 0)
 713
 714     def test_svstep_inner_loop_8_jl(self):
 715         """tests svstep inner loop, running 8 times (sv.setvl.), checking
 716             jl is copied into a *Vector* result.
 717
 718             fuuun...
 719         """
 720         lst = SVP64Asm([
 721                         # set DCT triple butterfly mode with persistent "REMAP"
 722                         "svshape 8, 1, 1, 2, 0",
 723                         "svremap 0, 0, 0, 2, 0, 1, 1",
 724                         "sv.svstep *2, 4, 1", # svstep get vector of ci
 725                         "sv.svstep *16, 3, 1", # svstep get vector of step
 726                         ])
 727         lst = list(lst)
 728
 729         # SVSTATE
 730         svstate = SVP64State()
 731         #svstate.vl = 2 # VL
 732         #svstate.maxvl = 2 # MAXVL
 733         print ("SVSTATE", bin(svstate.asint()))
 734
 735         with Program(lst, bigendian=False) as program:
 736             sim = self.run_tst_program(program, svstate=svstate)
 737             print ("SVSTATE after", bin(sim.svstate.asint()))
 738             print ("        vl", bin(sim.svstate.vl))
 739             print ("        mvl", bin(sim.svstate.maxvl))
 740             print ("    srcstep", bin(sim.svstate.srcstep))
 741             print ("    dststep", bin(sim.svstate.dststep))
 742             print ("     vfirst", bin(sim.svstate. vfirst))
 743             self.assertEqual(sim.svstate.vl, 12)
 744             self.assertEqual(sim.svstate.maxvl, 12)
 745             # svstep called four times, reset occurs, srcstep zero
 746             self.assertEqual(sim.svstate.srcstep, 0)
 747             self.assertEqual(sim.svstate.dststep, 0)
 748             for i in range(4):
 749                 self.assertEqual(sim.gpr(2+i), SelectableInt(8, 64))
 750                 self.assertEqual(sim.gpr(6+i), SelectableInt(4, 64))
 751                 self.assertEqual(sim.gpr(10+i), SelectableInt(2, 64))
 752                 self.assertEqual(sim.gpr(16+i), SelectableInt(i, 64))
 753                 self.assertEqual(sim.gpr(24+i), SelectableInt(0, 64))
 754             for i in range(2):
 755                 self.assertEqual(sim.gpr(20+i), SelectableInt(i, 64))
 756                 self.assertEqual(sim.gpr(22+i), SelectableInt(i, 64))
 757             self.assertEqual(sim.svstate.vfirst, 0)
 758             CR0 = sim.crl[0]
 759             print("      CR0", bin(CR0.get_range().value))
 760             self.assertEqual(CR0[CRFields.EQ], 0)
 761             self.assertEqual(CR0[CRFields.LT], 0)
 762             self.assertEqual(CR0[CRFields.GT], 0)
 763             self.assertEqual(CR0[CRFields.SO], 0)
 764
 765     def test_sv_add(self):
 766         """sets VL=2 then adds:
 767            * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 768            * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 769         """
 770         isa = SVP64Asm(["setvl 0, 0, 2, 0, 1, 1",
 771                         'sv.add *1, *5, *9',
 772                         "setvl 3, 0, 0, 0, 0, 0",
 773                        ])
 774         lst = list(isa)
 775         print ("listing", lst)
 776
 777         # initial values in GPR regfile
 778         initial_regs = [0] * 32
 779         initial_regs[9] = 0x1234
 780         initial_regs[10] = 0x1111
 781         initial_regs[5] = 0x4321
 782         initial_regs[6] = 0x2223
 783
 784         # copy before running
 785         expected_regs = deepcopy(initial_regs)
 786         expected_regs[1] = 0x5555
 787         expected_regs[2] = 0x3334
 788         expected_regs[3] = 2       # setvl places copy of VL here
 789
 790         with Program(lst, bigendian=False) as program:
 791             sim = self.run_tst_program(program, initial_regs)
 792             self._check_regs(sim, expected_regs)
 793
 794     def test_svstep_add_1(self):
 795         """tests svstep with an add, when it reaches VL
 796         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 797                         'sv.add *1, *5, *9',
 798                         "setvl. 0, 0, 1, 1, 0, 0",
 799                         'sv.add *1, *5, *9',
 800                         "setvl. 3, 0, 1, 1, 0, 0"
 801                         ])
 802         sequence is as follows:
 803         * setvl sets VL=2 but also "Vertical First" mode.
 804           this sets SVSTATE[SVF].
 805         * first add, which has srcstep/dststep = 0, does add 1,5,9
 806         * svstep EXPLICITLY walks srcstep/dststep to next element
 807         * second add, which now has srcstep/dststep = 1, does add 2,6,10
 808         * svstep EXPLICITLY walks srcstep/dststep to next element,
 809           which now equals VL.  srcstep and dststep are both set to
 810           zero
 811         """
 812         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 813                         'sv.add *1, *5, *9',
 814                         "setvl. 0, 0, 1, 1, 0, 0",  # svstep
 815                         'sv.add *1, *5, *9',
 816                         "setvl. 3, 0, 1, 1, 0, 0", # svstep
 817                         "setvl 4, 0, 0, 0, 0, 0"  # svstep
 818                         ])
 819         lst = list(lst)
 820
 821         # SVSTATE (in this case, VL=2)
 822         svstate = SVP64State()
 823         svstate.vl = 2 # VL
 824         svstate.maxvl = 2 # MAXVL
 825         print ("SVSTATE", bin(svstate.asint()))
 826
 827         # initial values in GPR regfile
 828         initial_regs = [0] * 32
 829         initial_regs[9] = 0x1234
 830         initial_regs[10] = 0x1111
 831         initial_regs[5] = 0x4321
 832         initial_regs[6] = 0x2223
 833
 834         # copy before running
 835         expected_regs = deepcopy(initial_regs)
 836         expected_regs[1] = 0x5555
 837         expected_regs[2] = 0x3334
 838         expected_regs[4] = 2       # setvl places copy of VL here
 839
 840         with Program(lst, bigendian=False) as program:
 841             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 842             print ("SVSTATE after", bin(sim.svstate.asint()))
 843             print ("        vl", bin(sim.svstate.vl))
 844             print ("        mvl", bin(sim.svstate.maxvl))
 845             print ("    srcstep", bin(sim.svstate.srcstep))
 846             print ("    dststep", bin(sim.svstate.dststep))
 847             print ("     vfirst", bin(sim.svstate. vfirst))
 848             self.assertEqual(sim.svstate.vl, 2)
 849             self.assertEqual(sim.svstate.maxvl, 2)
 850             self.assertEqual(sim.svstate.srcstep, 0)
 851             self.assertEqual(sim.svstate.dststep, 0)
 852             # when end reached, vertical mode is exited
 853             self.assertEqual(sim.svstate.vfirst, 0)
 854             CR0 = sim.crl[0]
 855             print("      CR0", bin(CR0.get_range().value))
 856             self.assertEqual(CR0[CRFields.EQ], 0)
 857             self.assertEqual(CR0[CRFields.LT], 0)
 858             self.assertEqual(CR0[CRFields.GT], 0)
 859             self.assertEqual(CR0[CRFields.SO], 1)
 860
 861             # check registers as expected
 862             self._check_regs(sim, expected_regs)
 863
 864     def test_svstep_add_2(self):
 865         """tests svstep with a branch.
 866         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 867                         'sv.add *1, *5, *9',
 868                         "setvl. 0, 0, 1, 1, 0, 0",
 869                         "bc 6, 3, -0xc"
 870                         ])
 871         sequence is as follows:
 872         * setvl sets VL=2 but also "Vertical First" mode.
 873           this sets MSR[SVF].
 874         * first time add, which has srcstep/dststep = 0, does add 1,5,9
 875         * svstep EXPLICITLY walks srcstep/dststep to next element,
 876           not yet met VL, so CR0.EQ is set to zero
 877         * branch conditional checks bne on CR0, jumps back TWELVE bytes
 878           because whilst branch is 32-bit the sv.add is 64-bit
 879         * second time add, which now has srcstep/dststep = 1, does add 2,6,10
 880         * svstep walks to next element, meets VL, so:
 881           - srcstep and dststep set to zero
 882           - CR0.EQ set to one
 883           - MSR[SVF] is cleared
 884         * branch conditional detects CR0.EQ=1 and FAILs the condition,
 885           therefore loop ends.
 886
 887         we therefore have an explicit "Vertical-First" system which can
 888         have **MULTIPLE* instructions inside a loop, running each element 0
 889         first, then looping back and running all element 1, then all element 2
 890         etc.
 891         """
 892         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 893                         'sv.add *1, *5, *9',
 894                         "setvl. 0, 0, 1, 1, 0, 0", # svstep - this is 64-bit!
 895                         "bc 6, 3, -0xc" # branch to add (64-bit op so -0xc!)
 896                         ])
 897         lst = list(lst)
 898
 899         # SVSTATE (in this case, VL=2)
 900         svstate = SVP64State()
 901         svstate.vl = 2 # VL
 902         svstate.maxvl = 2 # MAXVL
 903         print ("SVSTATE", bin(svstate.asint()))
 904
 905         # initial values in GPR regfile
 906         initial_regs = [0] * 32
 907         initial_regs[9] = 0x1234
 908         initial_regs[10] = 0x1111
 909         initial_regs[5] = 0x4321
 910         initial_regs[6] = 0x2223
 911
 912         # copy before running
 913         expected_regs = deepcopy(initial_regs)
 914         expected_regs[1] = 0x5555
 915         expected_regs[2] = 0x3334
 916
 917         with Program(lst, bigendian=False) as program:
 918             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 919             print ("SVSTATE after", bin(sim.svstate.asint()))
 920             print ("        vl", bin(sim.svstate.vl))
 921             print ("        mvl", bin(sim.svstate.maxvl))
 922             print ("    srcstep", bin(sim.svstate.srcstep))
 923             print ("    dststep", bin(sim.svstate.dststep))
 924             print ("     vfirst", bin(sim.svstate. vfirst))
 925             self.assertEqual(sim.svstate.vl, 2)
 926             self.assertEqual(sim.svstate.maxvl, 2)
 927             self.assertEqual(sim.svstate.srcstep, 0)
 928             self.assertEqual(sim.svstate.dststep, 0)
 929             # when end reached, vertical mode is exited
 930             self.assertEqual(sim.svstate.vfirst, 0)
 931             CR0 = sim.crl[0]
 932             print("      CR0", bin(CR0.get_range().value))
 933             self.assertEqual(CR0[CRFields.EQ], 0)
 934             self.assertEqual(CR0[CRFields.LT], 0)
 935             self.assertEqual(CR0[CRFields.GT], 0)
 936             self.assertEqual(CR0[CRFields.SO], 1)
 937
 938             # check registers as expected
 939             self._check_regs(sim, expected_regs)
 940
 941     def test_svremap(self):
 942         """svremap, see if values get set
 943         """
 944         lst = SVP64Asm(["svremap 11, 0, 1, 2, 3, 3, 1",
 945                         ])
 946         lst = list(lst)
 947
 948         with Program(lst, bigendian=False) as program:
 949             sim = self.run_tst_program(program)
 950             svstate = sim.svstate
 951             print ("SVREMAP after", bin(svstate.value))
 952             print ("        men", bin(svstate.SVme))
 953             print ("        mi0", bin(svstate.mi0))
 954             print ("        mi1", bin(svstate.mi1))
 955             print ("        mi2", bin(svstate.mi2))
 956             print ("        mo0", bin(svstate.mo0))
 957             print ("        mo1", bin(svstate.mo1))
 958             print ("    persist", bin(svstate.RMpst))
 959             self.assertEqual(svstate.SVme, 11)
 960             self.assertEqual(svstate.mi0, 0)
 961             self.assertEqual(svstate.mi1, 1)
 962             self.assertEqual(svstate.mi2, 2)
 963             self.assertEqual(svstate.mo0, 3)
 964             self.assertEqual(svstate.mo1, 3)
 965             self.assertEqual(svstate.RMpst, 1)
 966
 967     def test_svstep_iota(self):
 968         """tests svstep "straight", placing srcstep, dststep into vector
 969         """
 970         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
 971                         "sv.svstep *0, 5, 1", # svstep get vector srcstep
 972                         "sv.svstep. *4, 6, 1", # svstep get vector dststep
 973                         ])
 974         lst = list(lst)
 975
 976         # SVSTATE
 977         svstate = SVP64State()
 978         #svstate.vl = 2 # VL
 979         #svstate.maxvl = 2 # MAXVL
 980         print ("SVSTATE", bin(svstate.asint()))
 981
 982         with Program(lst, bigendian=False) as program:
 983             sim = self.run_tst_program(program, svstate=svstate)
 984             print ("SVSTATE after", bin(sim.svstate.asint()))
 985             print ("        vl", bin(sim.svstate.vl))
 986             print ("        mvl", bin(sim.svstate.maxvl))
 987             print ("    srcstep", bin(sim.svstate.srcstep))
 988             print ("    dststep", bin(sim.svstate.dststep))
 989             print ("     vfirst", bin(sim.svstate. vfirst))
 990             self.assertEqual(sim.svstate.vl, 4)
 991             self.assertEqual(sim.svstate.maxvl, 4)
 992             # svstep called four times, reset occurs, srcstep zero
 993             self.assertEqual(sim.svstate.srcstep, 0)
 994             self.assertEqual(sim.svstate.dststep, 0)
 995             for i in range(4):
 996                 self.assertEqual(sim.gpr(0+i), SelectableInt(i, 64))
 997                 self.assertEqual(sim.gpr(4+i), SelectableInt(i, 64))
 998             self.assertEqual(sim.svstate.vfirst, 0)
 999             CR0 = sim.crl[0]
1000             print("      CR0", bin(CR0.get_range().value))
1001             self.assertEqual(CR0[CRFields.EQ], 0)
1002             self.assertEqual(CR0[CRFields.LT], 0)
1003             self.assertEqual(CR0[CRFields.GT], 0)
1004             self.assertEqual(CR0[CRFields.SO], 1)
1005
1006     def test_svstep_iota_mask(self):
1007         """tests svstep "straight", placing srcstep, dststep into vector
1008         """
1009         lst = SVP64Asm(["setvl 0, 0, 5, 0, 1, 1",
1010                         "sv.svstep/m=r30 *0, 5, 1", # svstep get vector srcstep
1011                         "sv.svstep./m=r30 *8, 6, 1", # svstep get vector dststep
1012                         ])
1013         lst = list(lst)
1014
1015         # SVSTATE
1016         svstate = SVP64State()
1017         #svstate.vl = 2 # VL
1018         #svstate.maxvl = 2 # MAXVL
1019         print ("SVSTATE", bin(svstate.asint()))
1020
1021         mask = 0b10101
1022         initial_regs = [0] * 32
1023         initial_regs[30] = mask
1024
1025         with Program(lst, bigendian=False) as program:
1026             sim = self.run_tst_program(program, svstate=svstate,
1027                                        initial_regs=initial_regs)
1028             print ("SVSTATE after", bin(sim.svstate.asint()))
1029             print ("        vl", bin(sim.svstate.vl))
1030             print ("        mvl", bin(sim.svstate.maxvl))
1031             print ("    srcstep", bin(sim.svstate.srcstep))
1032             print ("    dststep", bin(sim.svstate.dststep))
1033             print ("     vfirst", bin(sim.svstate. vfirst))
1034             self.assertEqual(sim.svstate.vl, 5)
1035             self.assertEqual(sim.svstate.maxvl, 5)
1036             # svstep called four times, reset occurs, srcstep zero
1037             self.assertEqual(sim.svstate.srcstep, 0)
1038             self.assertEqual(sim.svstate.dststep, 0)
1039             sim.gpr.dump()
1040             for i in range(5):
1041                 if mask & (1<<i):
1042                     tst = i
1043                 else:
1044                     tst = 0
1045                 self.assertEqual(sim.gpr(0+i), SelectableInt(tst, 64))
1046                 self.assertEqual(sim.gpr(8+i), SelectableInt(tst, 64))
1047             self.assertEqual(sim.svstate.vfirst, 0)
1048             CR4 = sim.crl[4]
1049             print("      CR4", bin(CR4.get_range().value))
1050             self.assertEqual(CR4[CRFields.EQ], 0)
1051             self.assertEqual(CR4[CRFields.LT], 0)
1052             self.assertEqual(CR4[CRFields.GT], 0)
1053             self.assertEqual(CR4[CRFields.SO], 0)
1054
1055     def run_tst_program(self, prog, initial_regs=None,
1056                               svstate=None,
1057                               initial_sprs=None):
1058         if initial_regs is None:
1059             initial_regs = [0] * 32
1060         simulator = run_tst(prog, initial_regs, svstate=svstate,
1061                               initial_sprs=initial_sprs)
1062         simulator.gpr.dump()
1063         return simulator
1064
1065
1066 if __name__ == "__main__":
1067     unittest.main()
1068