src/openpower/decoder/isa/test_caller_setvl.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.decoder.isa.caller import CRFields, SVP64State
   6 from openpower.decoder.isa.test_caller import run_tst
   7 from openpower.decoder.selectable_int import SelectableInt
   8 from openpower.simulator.program import Program
   9 from openpower.sv.trans.svp64 import SVP64Asm
  10
  11
  12 class DecoderTestCase(FHDLTestCase):
  13
  14     def _check_regs(self, sim, expected):
  15         print("GPR")
  16         sim.gpr.dump()
  17         for i in range(32):
  18             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  19
  20     def test_1_setvl_zero_rc1(self):
  21         lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1",
  22                         ])
  23         lst = list(lst)
  24
  25         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
  26         # but, ha! r4 (RA) is zero. and Rc=1. therefore, CR0 should be set EQ
  27         svstate = SVP64State()
  28         svstate.maxvl = 5  # MAXVL
  29         print("SVSTATE", bin(svstate.asint()))
  30
  31         with Program(lst, bigendian=False) as program:
  32             sim = self.run_tst_program(program, svstate=svstate)
  33             print("SVSTATE after", bin(sim.svstate.asint()))
  34             print("        vl", bin(sim.svstate.vl))
  35             print("        mvl", bin(sim.svstate.maxvl))
  36             print("    srcstep", bin(sim.svstate.srcstep))
  37             print("    dststep", bin(sim.svstate.dststep))
  38             print("     vfirst", bin(sim.svstate.vfirst))
  39             self.assertEqual(sim.svstate.vl, 0)
  40             self.assertEqual(sim.svstate.maxvl, 5)
  41             self.assertEqual(sim.svstate.srcstep, 0)
  42             self.assertEqual(sim.svstate.dststep, 0)
  43             self.assertEqual(sim.svstate.vfirst, 0)
  44             print("      gpr4", sim.gpr(4))
  45             self.assertEqual(sim.gpr(4), SelectableInt(0, 64))
  46             print("      gpr5", sim.gpr(5))
  47             self.assertEqual(sim.gpr(5), SelectableInt(0, 64))
  48             CR0 = sim.crl[0]
  49             print("      CR0", bin(CR0.get_range().value))
  50             self.assertEqual(CR0[CRFields.EQ], 1)
  51             self.assertEqual(CR0[CRFields.LT], 0)
  52             self.assertEqual(CR0[CRFields.GT], 0)
  53             self.assertEqual(CR0[CRFields.SO], 0)
  54
  55     def test_2_setvl_nonzero_rc1(self):
  56         lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1",
  57                         ])
  58         lst = list(lst)
  59
  60         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
  61         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
  62         svstate = SVP64State()
  63         svstate.maxvl = 5  # MAXVL
  64         print("SVSTATE", bin(svstate.asint()))
  65
  66         initial_regs = [0] * 32
  67         initial_regs[4] = 4
  68
  69         with Program(lst, bigendian=False) as program:
  70             sim = self.run_tst_program(program, svstate=svstate,
  71                                        initial_regs=initial_regs)
  72             print("SVSTATE after", bin(sim.svstate.asint()))
  73             print("        vl", bin(sim.svstate.vl))
  74             print("        mvl", bin(sim.svstate.maxvl))
  75             print("    srcstep", bin(sim.svstate.srcstep))
  76             print("    dststep", bin(sim.svstate.dststep))
  77             print("     vfirst", bin(sim.svstate.vfirst))
  78             self.assertEqual(sim.svstate.vl, 4)
  79             self.assertEqual(sim.svstate.maxvl, 5)
  80             self.assertEqual(sim.svstate.srcstep, 0)
  81             self.assertEqual(sim.svstate.dststep, 0)
  82             self.assertEqual(sim.svstate.vfirst, 0)
  83             print("      gpr4", sim.gpr(4))
  84             self.assertEqual(sim.gpr(4), SelectableInt(4, 64))
  85             print("      gpr5", sim.gpr(5))
  86             self.assertEqual(sim.gpr(5), SelectableInt(4, 64))
  87             CR0 = sim.crl[0]
  88             print("      CR0", bin(CR0.get_range().value))
  89             self.assertEqual(CR0[CRFields.EQ], 0)
  90             self.assertEqual(CR0[CRFields.LT], 0)
  91             self.assertEqual(CR0[CRFields.GT], 1)
  92             self.assertEqual(CR0[CRFields.SO], 0)
  93
  94     def test_3_setvl_overflow_rc1(self):
  95         lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1",
  96                         ])
  97         lst = list(lst)
  98
  99         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 100         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 101         svstate = SVP64State()
 102         svstate.maxvl = 5  # MAXVL
 103         print("SVSTATE", bin(svstate.asint()))
 104
 105         initial_regs = [0] * 32
 106         initial_regs[4] = 1000  # much greater than MAXVL
 107
 108         with Program(lst, bigendian=False) as program:
 109             sim = self.run_tst_program(program, svstate=svstate,
 110                                        initial_regs=initial_regs)
 111             print("SVSTATE after", bin(sim.svstate.asint()))
 112             print("        vl", bin(sim.svstate.vl))
 113             print("        mvl", bin(sim.svstate.maxvl))
 114             print("    srcstep", bin(sim.svstate.srcstep))
 115             print("    dststep", bin(sim.svstate.dststep))
 116             print("     vfirst", bin(sim.svstate.vfirst))
 117             self.assertEqual(sim.svstate.vl, 5)
 118             self.assertEqual(sim.svstate.maxvl, 5)
 119             self.assertEqual(sim.svstate.srcstep, 0)
 120             self.assertEqual(sim.svstate.dststep, 0)
 121             self.assertEqual(sim.svstate.vfirst, 0)
 122             print("      gpr4", sim.gpr(4))
 123             self.assertEqual(sim.gpr(4), SelectableInt(1000, 64))  # unmodified
 124             print("      gpr5", sim.gpr(5))
 125             self.assertEqual(sim.gpr(5), SelectableInt(5, 64)
 126                              )  # equal to MAXVL
 127             CR0 = sim.crl[0]
 128             print("      CR0", bin(CR0.get_range().value))
 129             self.assertEqual(CR0[CRFields.EQ], 0)
 130             self.assertEqual(CR0[CRFields.LT], 0)
 131             self.assertEqual(CR0[CRFields.GT], 1)
 132             self.assertEqual(CR0[CRFields.SO], 1)
 133
 134     def test_4_setvl_max_overflow_rc1(self):
 135         """this should set overflow even though VL gets set to MAXVL
 136         at its limit of 127 (0b1111111)
 137         """
 138         lst = SVP64Asm(["setvl. 5, 4, 127, 0, 1, 1",
 139                         ])
 140         lst = list(lst)
 141
 142         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 143         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 144         svstate = SVP64State()
 145         svstate.maxvl = 5  # MAXVL
 146         print("SVSTATE", bin(svstate.asint()))
 147
 148         initial_regs = [0] * 32
 149         initial_regs[4] = 1000  # much greater than MAXVL
 150
 151         with Program(lst, bigendian=False) as program:
 152             sim = self.run_tst_program(program, svstate=svstate,
 153                                        initial_regs=initial_regs)
 154             print("SVSTATE after", bin(sim.svstate.asint()))
 155             print("        vl", bin(sim.svstate.vl))
 156             print("        mvl", bin(sim.svstate.maxvl))
 157             print("    srcstep", bin(sim.svstate.srcstep))
 158             print("    dststep", bin(sim.svstate.dststep))
 159             print("     vfirst", bin(sim.svstate.vfirst))
 160             self.assertEqual(sim.svstate.vl, 127)
 161             self.assertEqual(sim.svstate.maxvl, 127)
 162             self.assertEqual(sim.svstate.srcstep, 0)
 163             self.assertEqual(sim.svstate.dststep, 0)
 164             self.assertEqual(sim.svstate.vfirst, 0)
 165             print("      gpr4", sim.gpr(4))
 166             self.assertEqual(sim.gpr(4), SelectableInt(1000, 64))  # unmodified
 167             print("      gpr5", sim.gpr(5))
 168             self.assertEqual(sim.gpr(5), SelectableInt(127, 64))  # eq. MAXVL
 169             CR0 = sim.crl[0]
 170             print("      CR0", bin(CR0.get_range().value))
 171             self.assertEqual(CR0[CRFields.EQ], 0)
 172             self.assertEqual(CR0[CRFields.LT], 0)
 173             self.assertEqual(CR0[CRFields.GT], 1)
 174             self.assertEqual(CR0[CRFields.SO], 1)
 175
 176     def test_5_setvl_max_rc1(self):
 177         """this should not set when VL gets set to MAXVL
 178         at its limit of 127 (0b1111111)
 179         """
 180         lst = SVP64Asm(["setvl. 5, 4, 127, 0, 1, 1",
 181                         ])
 182         lst = list(lst)
 183
 184         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 185         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 186         svstate = SVP64State()
 187         svstate.maxvl = 5  # MAXVL
 188         print("SVSTATE", bin(svstate.asint()))
 189
 190         initial_regs = [0] * 32
 191         initial_regs[4] = 127  # exactly equal to MAXVL
 192
 193         with Program(lst, bigendian=False) as program:
 194             sim = self.run_tst_program(program, svstate=svstate,
 195                                        initial_regs=initial_regs)
 196             print("SVSTATE after", bin(sim.svstate.asint()))
 197             print("        vl", bin(sim.svstate.vl))
 198             print("        mvl", bin(sim.svstate.maxvl))
 199             print("    srcstep", bin(sim.svstate.srcstep))
 200             print("    dststep", bin(sim.svstate.dststep))
 201             print("     vfirst", bin(sim.svstate.vfirst))
 202             self.assertEqual(sim.svstate.vl, 127)
 203             self.assertEqual(sim.svstate.maxvl, 127)
 204             self.assertEqual(sim.svstate.srcstep, 0)
 205             self.assertEqual(sim.svstate.dststep, 0)
 206             self.assertEqual(sim.svstate.vfirst, 0)
 207             print("      gpr4", sim.gpr(4))
 208             self.assertEqual(sim.gpr(4), SelectableInt(127, 64))  # unmodified
 209             print("      gpr5", sim.gpr(5))
 210             self.assertEqual(sim.gpr(5), SelectableInt(127, 64))  # eq. MAXVL
 211             CR0 = sim.crl[0]
 212             print("      CR0", bin(CR0.get_range().value))
 213             self.assertEqual(CR0[CRFields.EQ], 0)
 214             self.assertEqual(CR0[CRFields.LT], 0)
 215             self.assertEqual(CR0[CRFields.GT], 1)
 216             self.assertEqual(CR0[CRFields.SO], 0)
 217
 218     def test_5_setvl_rt0_rc1(self):
 219         """odd one. Rc=1, RT=0, RA!=0, so RT does not get set, but VL does.
 220         confirms that when Rc=1 and RT is unmodified that CR0 still is updated
 221         """
 222         lst = SVP64Asm(["setvl. 0, 4, 5, 0, 1, 1",
 223                         ])
 224         lst = list(lst)
 225
 226         # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
 227         # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
 228         svstate = SVP64State()
 229         svstate.maxvl = 5  # MAXVL
 230         print("SVSTATE", bin(svstate.asint()))
 231
 232         initial_regs = [0] * 32
 233         initial_regs[4] = 127  # overlimit, should set CR0.SO=1, and CR0.GT=1
 234
 235         with Program(lst, bigendian=False) as program:
 236             sim = self.run_tst_program(program, svstate=svstate,
 237                                        initial_regs=initial_regs)
 238             print("SVSTATE after", bin(sim.svstate.asint()))
 239             print("        vl", bin(sim.svstate.vl))
 240             print("        mvl", bin(sim.svstate.maxvl))
 241             print("    srcstep", bin(sim.svstate.srcstep))
 242             print("    dststep", bin(sim.svstate.dststep))
 243             print("     vfirst", bin(sim.svstate.vfirst))
 244             self.assertEqual(sim.svstate.vl, 5)
 245             self.assertEqual(sim.svstate.maxvl, 5)
 246             self.assertEqual(sim.svstate.srcstep, 0)
 247             self.assertEqual(sim.svstate.dststep, 0)
 248             self.assertEqual(sim.svstate.vfirst, 0)
 249             print("      gpr0", sim.gpr(0))
 250             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))  # unmodified
 251             print("      gpr4", sim.gpr(4))
 252             self.assertEqual(sim.gpr(4), SelectableInt(127, 64))  # unmodified
 253             CR0 = sim.crl[0]
 254             print("      CR0", bin(CR0.get_range().value))
 255             self.assertEqual(CR0[CRFields.EQ], 0)
 256             self.assertEqual(CR0[CRFields.LT], 0)
 257             self.assertEqual(CR0[CRFields.GT], 1)
 258             self.assertEqual(CR0[CRFields.SO], 1)
 259
 260     def test_sv_sv_setvl(self):
 261         """test sv.setvl instruction works.  WARNING, going beyond
 262         RT=0..31 does not work, bug in PowerDecoder2 / ISACaller,
 263         related to RT_OR_ZERO and to simplev.mdwn pseudocode having
 264         _RT not be EXTRA-extended properly
 265         """
 266         lst = SVP64Asm(["sv.setvl 8, 31, 10, 0, 1, 1",  # setvl into RT=8
 267                         ])
 268         lst = list(lst)
 269
 270         # SVSTATE (in this case, VL=4) which is going to get erased by setvl
 271         svstate = SVP64State()
 272         svstate.vl = 4  # VL
 273         svstate.maxvl = 4  # MAXVL
 274         print("SVSTATE", bin(svstate.asint()))
 275
 276         initial_regs = [0] * 64
 277         initial_regs[31] = 200
 278
 279         with Program(lst, bigendian=False) as program:
 280             sim = self.run_tst_program(program, initial_regs=initial_regs,
 281                                        svstate=svstate)
 282             print("SVSTATE after", bin(sim.svstate.asint()))
 283             print("        vl", bin(sim.svstate.vl))
 284             print("        mvl", bin(sim.svstate.maxvl))
 285             print("    srcstep", bin(sim.svstate.srcstep))
 286             print("    dststep", bin(sim.svstate.dststep))
 287             print("     vfirst", bin(sim.svstate.vfirst))
 288             self.assertEqual(sim.svstate.vl, 10)
 289             self.assertEqual(sim.svstate.maxvl, 10)
 290             self.assertEqual(sim.svstate.srcstep, 0)
 291             self.assertEqual(sim.svstate.dststep, 0)
 292             self.assertEqual(sim.svstate.vfirst, 0)
 293             print("      gpr31", sim.gpr(31))
 294             print("      gpr8", sim.gpr(8))
 295             self.assertEqual(sim.gpr(8), SelectableInt(10, 64))
 296
 297     def test_svstep_1(self):
 298         lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1",  # actual setvl (VF mode)
 299                         "svstep 0, 1, 0",  # svstep
 300                         "svstep 0, 1, 0",  # svstep
 301                         ])
 302         lst = list(lst)
 303
 304         # SVSTATE (in this case, VL=4) which is going to get erased by setvl
 305         svstate = SVP64State()
 306         svstate.vl = 4  # VL
 307         svstate.maxvl = 4  # MAXVL
 308         print("SVSTATE", bin(svstate.asint()))
 309
 310         with Program(lst, bigendian=False) as program:
 311             sim = self.run_tst_program(program, svstate=svstate)
 312             print("SVSTATE after", bin(sim.svstate.asint()))
 313             print("        vl", bin(sim.svstate.vl))
 314             print("        mvl", bin(sim.svstate.maxvl))
 315             print("    srcstep", bin(sim.svstate.srcstep))
 316             print("    dststep", bin(sim.svstate.dststep))
 317             print("     vfirst", bin(sim.svstate.vfirst))
 318             self.assertEqual(sim.svstate.vl, 10)
 319             self.assertEqual(sim.svstate.maxvl, 10)
 320             self.assertEqual(sim.svstate.srcstep, 2)
 321             self.assertEqual(sim.svstate.dststep, 2)
 322             self.assertEqual(sim.svstate.vfirst, 1)
 323             print("      gpr1", sim.gpr(0))
 324             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 325
 326     def test_svstep_2(self):
 327         """tests svstep when it reaches VL
 328         """
 329         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",  # actual setvl (VF mode)
 330                         "svstep. 0, 1, 0",  # svstep (Rc=1)
 331                         "svstep. 0, 1, 0",  # svstep (Rc=1)
 332                         ])
 333         lst = list(lst)
 334
 335         # SVSTATE (in this case, VL=2)
 336         svstate = SVP64State()
 337         svstate.vl = 2  # VL
 338         svstate.maxvl = 2  # MAXVL
 339         print("SVSTATE", bin(svstate.asint()))
 340
 341         with Program(lst, bigendian=False) as program:
 342             sim = self.run_tst_program(program, svstate=svstate)
 343             print("SVSTATE after", bin(sim.svstate.asint()))
 344             print("        vl", bin(sim.svstate.vl))
 345             print("        mvl", bin(sim.svstate.maxvl))
 346             print("    srcstep", bin(sim.svstate.srcstep))
 347             print("    dststep", bin(sim.svstate.dststep))
 348             print("     vfirst", bin(sim.svstate.vfirst))
 349             self.assertEqual(sim.svstate.vl, 2)
 350             self.assertEqual(sim.svstate.maxvl, 2)
 351             self.assertEqual(sim.svstate.srcstep, 0)
 352             self.assertEqual(sim.svstate.dststep, 0)
 353             # when end reached, vertical mode is exited
 354             self.assertEqual(sim.svstate.vfirst, 0)
 355             print("      gpr1", sim.gpr(0))
 356             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 357             CR0 = sim.crl[0]
 358             print("      CR0", bin(CR0.get_range().value))
 359             self.assertEqual(CR0[CRFields.EQ], 0)
 360             self.assertEqual(CR0[CRFields.LT], 0)
 361             self.assertEqual(CR0[CRFields.GT], 0)
 362             self.assertEqual(CR0[CRFields.SO], 1)
 363
 364     def test_svstep_3(self):
 365         """tests svstep when it *doesn't* reach VL
 366         """
 367         lst = SVP64Asm(["setvl 0, 0, 3, 1, 1, 1",  # actual setvl (VF mode)
 368                         "svstep. 0, 1, 0",  # svstep (Rc=1)
 369                         "svstep. 0, 1, 0",  # svstep (Rc=1)
 370                         ])
 371         lst = list(lst)
 372
 373         # SVSTATE (in this case, VL=2)
 374         svstate = SVP64State()
 375         svstate.vl = 2  # VL
 376         svstate.maxvl = 2  # MAXVL
 377         print("SVSTATE", bin(svstate.asint()))
 378
 379         with Program(lst, bigendian=False) as program:
 380             sim = self.run_tst_program(program, svstate=svstate)
 381             print("SVSTATE after", bin(sim.svstate.asint()))
 382             print("        vl", bin(sim.svstate.vl))
 383             print("        mvl", bin(sim.svstate.maxvl))
 384             print("    srcstep", bin(sim.svstate.srcstep))
 385             print("    dststep", bin(sim.svstate.dststep))
 386             print("     vfirst", bin(sim.svstate. vfirst))
 387             self.assertEqual(sim.svstate.vl, 3)
 388             self.assertEqual(sim.svstate.maxvl, 3)
 389             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 390             self.assertEqual(sim.svstate.srcstep, 2)
 391             self.assertEqual(sim.svstate.dststep, 2)
 392             print("      gpr1", sim.gpr(0))
 393             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 394             self.assertEqual(sim.svstate.vfirst, 1)
 395             CR0 = sim.crl[0]
 396             print("      CR0", bin(CR0.get_range().value))
 397             self.assertEqual(CR0[CRFields.EQ], 0)
 398             self.assertEqual(CR0[CRFields.LT], 0)
 399             self.assertEqual(CR0[CRFields.GT], 0)
 400             self.assertEqual(CR0[CRFields.SO], 0)
 401
 402     def test_setvl_ctr_1_rc1(self):
 403         """setvl CTR mode, with Rc=1, testing if VL and MVL are over-ridden
 404         and CR0 set correctly
 405         """
 406         lst = SVP64Asm(["setvl. 1, 0, 10, 0, 1, 1",
 407                         ])
 408         lst = list(lst)
 409
 410         # SVSTATE (in this case, VL=2), want to see if these get changed
 411         svstate = SVP64State()
 412         svstate.vl = 2  # VL
 413         svstate.maxvl = 2  # MAXVL
 414         print("SVSTATE", bin(svstate.asint()))
 415         sprs = {'CTR': 5,
 416                 }
 417
 418         with Program(lst, bigendian=False) as program:
 419             sim = self.run_tst_program(program, svstate=svstate,
 420                                        initial_sprs=sprs)
 421             print("SVSTATE after", bin(sim.svstate.asint()))
 422             print("        vl", bin(sim.svstate.vl))
 423             print("        mvl", bin(sim.svstate.maxvl))
 424             self.assertEqual(sim.svstate.vl, 5)
 425             self.assertEqual(sim.svstate.maxvl, 10)
 426             print("      gpr1", sim.gpr(1))
 427             self.assertEqual(sim.gpr(1), SelectableInt(5, 64))
 428
 429             CR0 = sim.crl[0]
 430             print("      CR0", bin(CR0.get_range().value))
 431             self.assertEqual(CR0[CRFields.EQ], 0)
 432             self.assertEqual(CR0[CRFields.LT], 0)
 433             self.assertEqual(CR0[CRFields.GT], 1)
 434             self.assertEqual(CR0[CRFields.SO], 0)
 435
 436     def test_setvl_ctr_1(self):
 437         """setvl CTR mode, testing if VL and MVL are over-ridden
 438         """
 439         lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1",
 440                         ])
 441         lst = list(lst)
 442
 443         # SVSTATE (in this case, VL=2), want to see if these get changed
 444         svstate = SVP64State()
 445         svstate.vl = 2  # VL
 446         svstate.maxvl = 2  # MAXVL
 447         print("SVSTATE", bin(svstate.asint()))
 448         sprs = {'CTR': 5,
 449                 }
 450
 451         with Program(lst, bigendian=False) as program:
 452             sim = self.run_tst_program(program, svstate=svstate,
 453                                        initial_sprs=sprs)
 454             print("SVSTATE after", bin(sim.svstate.asint()))
 455             print("        vl", bin(sim.svstate.vl))
 456             print("        mvl", bin(sim.svstate.maxvl))
 457             self.assertEqual(sim.svstate.vl, 5)
 458             self.assertEqual(sim.svstate.maxvl, 10)
 459             print("      gpr1", sim.gpr(1))
 460             self.assertEqual(sim.gpr(1), SelectableInt(5, 64))
 461
 462             CR0 = sim.crl[0]
 463             print("      CR0", bin(CR0.get_range().value))
 464             self.assertEqual(CR0[CRFields.EQ], 0)
 465             self.assertEqual(CR0[CRFields.LT], 0)
 466             self.assertEqual(CR0[CRFields.GT], 0)
 467             self.assertEqual(CR0[CRFields.SO], 0)
 468
 469     def test_setvl_ctr_2_rc1(self):
 470         """setvl Rc=1, CTR large, testing if VL and MVL are over-ridden,
 471         check if CR0.SO gets set
 472         """
 473         lst = SVP64Asm(["setvl. 1, 0, 10, 0, 1, 1",
 474                         ])
 475         lst = list(lst)
 476
 477         # SVSTATE (in this case, VL=2), want to see if these get changed
 478         svstate = SVP64State()
 479         svstate.vl = 2  # VL
 480         svstate.maxvl = 2  # MAXVL
 481         print("SVSTATE", bin(svstate.asint()))
 482         sprs = {'CTR': 0x1000000000,
 483                 }
 484
 485         with Program(lst, bigendian=False) as program:
 486             sim = self.run_tst_program(program, svstate=svstate,
 487                                        initial_sprs=sprs)
 488             print("SVSTATE after", bin(sim.svstate.asint()))
 489             print("        vl", bin(sim.svstate.vl))
 490             print("        mvl", bin(sim.svstate.maxvl))
 491             self.assertEqual(sim.svstate.vl, 10)
 492             self.assertEqual(sim.svstate.maxvl, 10)
 493             print("      gpr1", sim.gpr(1))
 494             self.assertEqual(sim.gpr(1), SelectableInt(10, 64))
 495
 496             CR0 = sim.crl[0]
 497             print("      CR0", bin(CR0.get_range().value))
 498             self.assertEqual(CR0[CRFields.EQ], 0)
 499             self.assertEqual(CR0[CRFields.LT], 0)
 500             self.assertEqual(CR0[CRFields.GT], 1)
 501             self.assertEqual(CR0[CRFields.SO], 1)
 502
 503     def test_setvl_ctr_2(self):
 504         """setvl CTR large, testing if VL and MVL are over-ridden
 505         """
 506         lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1",
 507                         ])
 508         lst = list(lst)
 509
 510         # SVSTATE (in this case, VL=2), want to see if these get changed
 511         svstate = SVP64State()
 512         svstate.vl = 2  # VL
 513         svstate.maxvl = 2  # MAXVL
 514         print("SVSTATE", bin(svstate.asint()))
 515         sprs = {'CTR': 0x1000000000,
 516                 }
 517
 518         with Program(lst, bigendian=False) as program:
 519             sim = self.run_tst_program(program, svstate=svstate,
 520                                        initial_sprs=sprs)
 521             print("SVSTATE after", bin(sim.svstate.asint()))
 522             print("        vl", bin(sim.svstate.vl))
 523             print("        mvl", bin(sim.svstate.maxvl))
 524             self.assertEqual(sim.svstate.vl, 10)
 525             self.assertEqual(sim.svstate.maxvl, 10)
 526             print("      gpr1", sim.gpr(1))
 527             self.assertEqual(sim.gpr(1), SelectableInt(10, 64))
 528
 529     def test_setvl_1(self):
 530         """straight setvl, testing if VL and MVL are over-ridden
 531         """
 532         lst = SVP64Asm(["setvl 0, 0, 10, 0, 1, 1",
 533                         ])
 534         lst = list(lst)
 535
 536         # SVSTATE (in this case, VL=2), want to see if these get changed
 537         svstate = SVP64State()
 538         svstate.vl = 2  # VL
 539         svstate.maxvl = 2  # MAXVL
 540         print("SVSTATE", bin(svstate.asint()))
 541
 542         with Program(lst, bigendian=False) as program:
 543             sim = self.run_tst_program(program, svstate=svstate)
 544             print("SVSTATE after", bin(sim.svstate.asint()))
 545             print("        vl", bin(sim.svstate.vl))
 546             print("        mvl", bin(sim.svstate.maxvl))
 547             self.assertEqual(sim.svstate.vl, 10)
 548             self.assertEqual(sim.svstate.maxvl, 10)
 549             print("      gpr1", sim.gpr(1))
 550             self.assertEqual(sim.gpr(1), SelectableInt(0, 64))
 551
 552     def test_setvl_2(self):
 553         """setvl, testing if VL is transferred to RT, and MVL truncates it
 554         """
 555         lst = SVP64Asm(["setvl 1, 0, 2, 0, 0, 1",
 556                         ])
 557         lst = list(lst)
 558
 559         # SVSTATE (in this case, VL=2), want to see if these get changed
 560         svstate = SVP64State()
 561         svstate.vl = 10  # VL
 562         svstate.maxvl = 10  # MAXVL
 563         print("SVSTATE", bin(svstate.asint()))
 564
 565         with Program(lst, bigendian=False) as program:
 566             sim = self.run_tst_program(program, svstate=svstate)
 567             print("SVSTATE after", bin(sim.svstate.asint()))
 568             print("        vl", bin(sim.svstate.vl))
 569             print("        mvl", bin(sim.svstate.maxvl))
 570             self.assertEqual(sim.svstate.maxvl, 2)
 571             self.assertEqual(sim.svstate.vl, 2)
 572             print("      gpr1", sim.gpr(1))
 573             self.assertEqual(sim.gpr(1), SelectableInt(2, 64))
 574
 575     def test_svstep_inner_loop_6(self):
 576         """tests svstep inner loop, running 6 times, looking for "k".
 577         also sees if k is actually output into reg 2 (RT=2)
 578         """
 579         lst = SVP64Asm([
 580             # set triple butterfly mode with persistent "REMAP"
 581             "svshape 8, 1, 1, 1, 1",
 582             "svremap 31, 1, 0, 2, 0, 1, 1",
 583             "svstep. 0, 2, 0",  # svstep (Rc=1)
 584             "svstep. 0, 2, 0",  # svstep (Rc=1)
 585             "svstep. 0, 2, 0",  # svstep (Rc=1)
 586             "svstep. 0, 2, 0",  # svstep (Rc=1)
 587             "svstep. 0, 2, 0",  # svstep (Rc=1)
 588             "svstep. 2, 2, 0",  # svstep (Rc=1)
 589         ])
 590         lst = list(lst)
 591
 592         # SVSTATE
 593         svstate = SVP64State()
 594         # svstate.vl = 2 # VL
 595         # svstate.maxvl = 2 # MAXVL
 596         print("SVSTATE", bin(svstate.asint()))
 597
 598         with Program(lst, bigendian=False) as program:
 599             sim = self.run_tst_program(program, svstate=svstate)
 600             print("SVSTATE after", bin(sim.svstate.asint()))
 601             print("        vl", bin(sim.svstate.vl))
 602             print("        mvl", bin(sim.svstate.maxvl))
 603             print("    srcstep", bin(sim.svstate.srcstep))
 604             print("    dststep", bin(sim.svstate.dststep))
 605             print("     vfirst", bin(sim.svstate. vfirst))
 606             self.assertEqual(sim.svstate.vl, 12)
 607             self.assertEqual(sim.svstate.maxvl, 12)
 608             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 609             self.assertEqual(sim.svstate.srcstep, 6)
 610             self.assertEqual(sim.svstate.dststep, 6)
 611             self.assertEqual(sim.gpr(2), SelectableInt(1, 64))
 612             self.assertEqual(sim.svstate.vfirst, 1)
 613             CR0 = sim.crl[0]
 614             print("      CR0", bin(CR0.get_range().value))
 615             self.assertEqual(CR0[CRFields.EQ], 0)
 616             self.assertEqual(CR0[CRFields.LT], 1)
 617             self.assertEqual(CR0[CRFields.GT], 1)
 618             self.assertEqual(CR0[CRFields.SO], 0)
 619
 620     def test_svstep_inner_loop_3(self):
 621         """tests svstep inner loop, running 3 times
 622         """
 623         lst = SVP64Asm([
 624             # set triple butterfly mode with persistent "REMAP"
 625             "svshape 8, 1, 1, 1, 1",
 626             "svremap 31, 1, 0, 2, 0, 1, 1",
 627             "svstep. 0, 2, 0",  # svstep (Rc=1)
 628             "svstep. 0, 2, 0",  # svstep (Rc=1)
 629             "svstep. 0, 2, 0",  # svstep (Rc=1)
 630         ])
 631         lst = list(lst)
 632
 633         # SVSTATE
 634         svstate = SVP64State()
 635         # svstate.vl = 2 # VL
 636         # svstate.maxvl = 2 # MAXVL
 637         print("SVSTATE", bin(svstate.asint()))
 638
 639         with Program(lst, bigendian=False) as program:
 640             sim = self.run_tst_program(program, svstate=svstate)
 641             print("SVSTATE after", bin(sim.svstate.asint()))
 642             print("        vl", bin(sim.svstate.vl))
 643             print("        mvl", bin(sim.svstate.maxvl))
 644             print("    srcstep", bin(sim.svstate.srcstep))
 645             print("    dststep", bin(sim.svstate.dststep))
 646             print("     vfirst", bin(sim.svstate. vfirst))
 647             self.assertEqual(sim.svstate.vl, 12)
 648             self.assertEqual(sim.svstate.maxvl, 12)
 649             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 650             self.assertEqual(sim.svstate.srcstep, 3)
 651             self.assertEqual(sim.svstate.dststep, 3)
 652             self.assertEqual(sim.gpr(0), SelectableInt(4, 64))
 653             self.assertEqual(sim.svstate.vfirst, 1)
 654             CR0 = sim.crl[0]
 655             print("      CR0", bin(CR0.get_range().value))
 656             self.assertEqual(CR0[CRFields.EQ], 0)
 657             self.assertEqual(CR0[CRFields.LT], 1)
 658             self.assertEqual(CR0[CRFields.GT], 1)
 659             self.assertEqual(CR0[CRFields.SO], 0)
 660
 661     def test_svstep_inner_loop_4(self):
 662         """tests svstep inner loop, running 4 times
 663         """
 664         lst = SVP64Asm([
 665             # set triple butterfly mode with persistent "REMAP"
 666             "svshape 8, 1, 1, 1, 1",
 667             "svremap 31, 1, 0, 2, 0, 1, 1",
 668             "svstep. 0, 2, 0",  # svstep (Rc=1)
 669             "svstep. 0, 2, 0",  # svstep (Rc=1)
 670             "svstep. 0, 2, 0",  # svstep (Rc=1)
 671             "svstep. 0, 2, 0",  # svstep (Rc=1)
 672         ])
 673         lst = list(lst)
 674
 675         # SVSTATE
 676         svstate = SVP64State()
 677         # svstate.vl = 2 # VL
 678         # svstate.maxvl = 2 # MAXVL
 679         print("SVSTATE", bin(svstate.asint()))
 680
 681         with Program(lst, bigendian=False) as program:
 682             sim = self.run_tst_program(program, svstate=svstate)
 683             print("SVSTATE after", bin(sim.svstate.asint()))
 684             print("        vl", bin(sim.svstate.vl))
 685             print("        mvl", bin(sim.svstate.maxvl))
 686             print("    srcstep", bin(sim.svstate.srcstep))
 687             print("    dststep", bin(sim.svstate.dststep))
 688             print("     vfirst", bin(sim.svstate. vfirst))
 689             self.assertEqual(sim.svstate.vl, 12)
 690             self.assertEqual(sim.svstate.maxvl, 12)
 691             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 692             self.assertEqual(sim.svstate.srcstep, 4)
 693             self.assertEqual(sim.svstate.dststep, 4)
 694             self.assertEqual(sim.gpr(0), SelectableInt(6, 64))
 695             self.assertEqual(sim.svstate.vfirst, 1)
 696             CR0 = sim.crl[0]
 697             print("      CR0", bin(CR0.get_range().value))
 698             self.assertEqual(CR0[CRFields.EQ], 0)
 699             self.assertEqual(CR0[CRFields.LT], 1)
 700             self.assertEqual(CR0[CRFields.GT], 0)
 701             self.assertEqual(CR0[CRFields.SO], 0)
 702
 703     def test_svstep_inner_loop_4_jl(self):
 704         """tests svstep inner loop, running 4 times, checking
 705            "jl" is returned after 4th iteration
 706         """
 707         lst = SVP64Asm([
 708             # set triple butterfly mode with persistent "REMAP"
 709             "svshape 8, 1, 1, 1, 1",
 710             "svremap 31, 1, 0, 2, 0, 1, 1",
 711             "svstep. 0, 2, 0",  # svstep (Rc=1)
 712             "svstep. 0, 2, 0",  # svstep (Rc=1)
 713             "svstep. 0, 2, 0",  # svstep (Rc=1)
 714             "svstep. 2, 2, 0",  # svstep (Rc=1)
 715         ])
 716         lst = list(lst)
 717
 718         # SVSTATE
 719         svstate = SVP64State()
 720         # svstate.vl = 2 # VL
 721         # svstate.maxvl = 2 # MAXVL
 722         print("SVSTATE", bin(svstate.asint()))
 723
 724         with Program(lst, bigendian=False) as program:
 725             sim = self.run_tst_program(program, svstate=svstate)
 726             print("SVSTATE after", bin(sim.svstate.asint()))
 727             print("        vl", bin(sim.svstate.vl))
 728             print("        mvl", bin(sim.svstate.maxvl))
 729             print("    srcstep", bin(sim.svstate.srcstep))
 730             print("    dststep", bin(sim.svstate.dststep))
 731             print("     vfirst", bin(sim.svstate. vfirst))
 732             self.assertEqual(sim.svstate.vl, 12)
 733             self.assertEqual(sim.svstate.maxvl, 12)
 734             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 735             self.assertEqual(sim.svstate.srcstep, 4)
 736             self.assertEqual(sim.svstate.dststep, 4)
 737             self.assertEqual(sim.gpr(2), SelectableInt(6, 64))
 738             self.assertEqual(sim.svstate.vfirst, 1)
 739             CR0 = sim.crl[0]
 740             print("      CR0", bin(CR0.get_range().value))
 741             self.assertEqual(CR0[CRFields.EQ], 0)
 742             self.assertEqual(CR0[CRFields.LT], 1)
 743             self.assertEqual(CR0[CRFields.GT], 0)
 744             self.assertEqual(CR0[CRFields.SO], 0)
 745
 746     def test_svstep_inner_loop_8_jl(self):
 747         """tests svstep inner loop, running 8 times (sv.setvl.), checking
 748             jl is copied into a *Vector* result.
 749
 750             fuuun...
 751         """
 752         lst = SVP64Asm([
 753             # set DCT triple butterfly mode with persistent "REMAP"
 754             "svshape 8, 1, 1, 2, 0",
 755             "svremap 0, 0, 0, 2, 0, 1, 1",
 756             "sv.svstep *2, 4, 1",  # svstep get vector of ci
 757             "sv.svstep *16, 3, 1",  # svstep get vector of step
 758         ])
 759         lst = list(lst)
 760
 761         # SVSTATE
 762         svstate = SVP64State()
 763         # svstate.vl = 2 # VL
 764         # svstate.maxvl = 2 # MAXVL
 765         print("SVSTATE", bin(svstate.asint()))
 766
 767         with Program(lst, bigendian=False) as program:
 768             sim = self.run_tst_program(program, svstate=svstate)
 769             print("SVSTATE after", bin(sim.svstate.asint()))
 770             print("        vl", bin(sim.svstate.vl))
 771             print("        mvl", bin(sim.svstate.maxvl))
 772             print("    srcstep", bin(sim.svstate.srcstep))
 773             print("    dststep", bin(sim.svstate.dststep))
 774             print("     vfirst", bin(sim.svstate. vfirst))
 775             self.assertEqual(sim.svstate.vl, 12)
 776             self.assertEqual(sim.svstate.maxvl, 12)
 777             # svstep called four times, reset occurs, srcstep zero
 778             self.assertEqual(sim.svstate.srcstep, 0)
 779             self.assertEqual(sim.svstate.dststep, 0)
 780             for i in range(4):
 781                 self.assertEqual(sim.gpr(2+i), SelectableInt(8, 64))
 782                 self.assertEqual(sim.gpr(6+i), SelectableInt(4, 64))
 783                 self.assertEqual(sim.gpr(10+i), SelectableInt(2, 64))
 784                 self.assertEqual(sim.gpr(16+i), SelectableInt(i, 64))
 785                 self.assertEqual(sim.gpr(24+i), SelectableInt(0, 64))
 786             for i in range(2):
 787                 self.assertEqual(sim.gpr(20+i), SelectableInt(i, 64))
 788                 self.assertEqual(sim.gpr(22+i), SelectableInt(i, 64))
 789             self.assertEqual(sim.svstate.vfirst, 0)
 790             CR0 = sim.crl[0]
 791             print("      CR0", bin(CR0.get_range().value))
 792             self.assertEqual(CR0[CRFields.EQ], 0)
 793             self.assertEqual(CR0[CRFields.LT], 0)
 794             self.assertEqual(CR0[CRFields.GT], 0)
 795             self.assertEqual(CR0[CRFields.SO], 0)
 796
 797     def test_sv_add(self):
 798         """sets VL=2 then adds:
 799            * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 800            * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 801         """
 802         isa = SVP64Asm(["setvl 0, 0, 2, 0, 1, 1",
 803                         'sv.add *1, *5, *9',
 804                         "setvl 3, 0, 0, 0, 0, 0",
 805                         ])
 806         lst = list(isa)
 807         print("listing", lst)
 808
 809         # initial values in GPR regfile
 810         initial_regs = [0] * 32
 811         initial_regs[9] = 0x1234
 812         initial_regs[10] = 0x1111
 813         initial_regs[5] = 0x4321
 814         initial_regs[6] = 0x2223
 815
 816         # copy before running
 817         expected_regs = deepcopy(initial_regs)
 818         expected_regs[1] = 0x5555
 819         expected_regs[2] = 0x3334
 820         expected_regs[3] = 2       # setvl places copy of VL here
 821
 822         with Program(lst, bigendian=False) as program:
 823             sim = self.run_tst_program(program, initial_regs)
 824             self._check_regs(sim, expected_regs)
 825
 826     def test_svstep_add_1(self):
 827         """tests svstep with an add, when it reaches VL
 828         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 829                         'sv.add *1, *5, *9',
 830                         "svstep. 0, 1, 0", # svstep (Rc=1)
 831                         "setvl. 0, 0, 1, 1, 0, 0",
 832                         'sv.add *1, *5, *9',
 833                         "svstep. 3, 1, 0", # svstep (Rc=1)
 834                         "setvl 4, 0, 0, 0, 0, 0", # getvl
 835                         ])
 836         sequence is as follows:
 837         * setvl sets VL=2 but also "Vertical First" mode.
 838           this sets SVSTATE[SVF].
 839         * first add, which has srcstep/dststep = 0, does add 1,5,9
 840         * svstep EXPLICITLY walks srcstep/dststep to next element
 841         * second add, which now has srcstep/dststep = 1, does add 2,6,10
 842         * svstep EXPLICITLY walks srcstep/dststep to next element,
 843           which now equals VL.  srcstep and dststep are both set to
 844           zero
 845         """
 846         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 847                         'sv.add *1, *5, *9',
 848                         "svstep. 0, 1, 0",  # svstep (Rc=1)
 849                         'sv.add *1, *5, *9',
 850                         "svstep. 3, 1, 0",  # svstep (Rc=1)
 851                         "setvl 4, 0, 0, 0, 0, 0",  # getvl
 852                         ])
 853         lst = list(lst)
 854
 855         # SVSTATE (in this case, VL=2)
 856         svstate = SVP64State()
 857         svstate.vl = 2  # VL
 858         svstate.maxvl = 2  # MAXVL
 859         print("SVSTATE", bin(svstate.asint()))
 860
 861         # initial values in GPR regfile
 862         initial_regs = [0] * 32
 863         initial_regs[9] = 0x1234
 864         initial_regs[10] = 0x1111
 865         initial_regs[5] = 0x4321
 866         initial_regs[6] = 0x2223
 867
 868         # copy before running
 869         expected_regs = deepcopy(initial_regs)
 870         expected_regs[1] = 0x5555
 871         expected_regs[2] = 0x3334
 872         expected_regs[4] = 2       # setvl places copy of VL here
 873
 874         with Program(lst, bigendian=False) as program:
 875             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 876             print("SVSTATE after", bin(sim.svstate.asint()))
 877             print("        vl", bin(sim.svstate.vl))
 878             print("        mvl", bin(sim.svstate.maxvl))
 879             print("    srcstep", bin(sim.svstate.srcstep))
 880             print("    dststep", bin(sim.svstate.dststep))
 881             print("     vfirst", bin(sim.svstate. vfirst))
 882             self.assertEqual(sim.svstate.vl, 2)
 883             self.assertEqual(sim.svstate.maxvl, 2)
 884             self.assertEqual(sim.svstate.srcstep, 0)
 885             self.assertEqual(sim.svstate.dststep, 0)
 886             # when end reached, vertical mode is exited
 887             self.assertEqual(sim.svstate.vfirst, 0)
 888             CR0 = sim.crl[0]
 889             print("      CR0", bin(CR0.get_range().value))
 890             self.assertEqual(CR0[CRFields.EQ], 0)
 891             self.assertEqual(CR0[CRFields.LT], 0)
 892             self.assertEqual(CR0[CRFields.GT], 0)
 893             self.assertEqual(CR0[CRFields.SO], 1)
 894
 895             # check registers as expected
 896             self._check_regs(sim, expected_regs)
 897
 898     def test_svstep_add_2(self):
 899         """tests svstep with a branch.
 900         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 901                         'sv.add *1, *5, *9',
 902                         "svstep. 0, 1, 0", # svstep (Rc=1)
 903                         "bc 6, 3, -0xc"
 904                         ])
 905         sequence is as follows:
 906         * setvl sets VL=2 but also "Vertical First" mode.
 907           this sets MSR[SVF].
 908         * first time add, which has srcstep/dststep = 0, does add 1,5,9
 909         * svstep EXPLICITLY walks srcstep/dststep to next element,
 910           not yet met VL, so CR0.EQ is set to zero
 911         * branch conditional checks bne on CR0, jumps back TWELVE bytes
 912           because whilst branch is 32-bit the sv.add is 64-bit
 913         * second time add, which now has srcstep/dststep = 1, does add 2,6,10
 914         * svstep walks to next element, meets VL, so:
 915           - srcstep and dststep set to zero
 916           - CR0.EQ set to one
 917           - MSR[SVF] is cleared
 918         * branch conditional detects CR0.EQ=1 and FAILs the condition,
 919           therefore loop ends.
 920
 921         we therefore have an explicit "Vertical-First" system which can
 922         have **MULTIPLE* instructions inside a loop, running each element 0
 923         first, then looping back and running all element 1, then all element 2
 924         etc.
 925         """
 926         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 927                         'sv.add *1, *5, *9',
 928                         "svstep. 0, 1, 0",  # svstep (Rc=1)
 929                         "bc 6, 3, -0xc"  # branch to add (64-bit op so -0xc!)
 930                         ])
 931         lst = list(lst)
 932
 933         # SVSTATE (in this case, VL=2)
 934         svstate = SVP64State()
 935         svstate.vl = 2  # VL
 936         svstate.maxvl = 2  # MAXVL
 937         print("SVSTATE", bin(svstate.asint()))
 938
 939         # initial values in GPR regfile
 940         initial_regs = [0] * 32
 941         initial_regs[9] = 0x1234
 942         initial_regs[10] = 0x1111
 943         initial_regs[5] = 0x4321
 944         initial_regs[6] = 0x2223
 945
 946         # copy before running
 947         expected_regs = deepcopy(initial_regs)
 948         expected_regs[1] = 0x5555
 949         expected_regs[2] = 0x3334
 950
 951         with Program(lst, bigendian=False) as program:
 952             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 953             print("SVSTATE after", bin(sim.svstate.asint()))
 954             print("        vl", bin(sim.svstate.vl))
 955             print("        mvl", bin(sim.svstate.maxvl))
 956             print("    srcstep", bin(sim.svstate.srcstep))
 957             print("    dststep", bin(sim.svstate.dststep))
 958             print("     vfirst", bin(sim.svstate. vfirst))
 959             self.assertEqual(sim.svstate.vl, 2)
 960             self.assertEqual(sim.svstate.maxvl, 2)
 961             self.assertEqual(sim.svstate.srcstep, 0)
 962             self.assertEqual(sim.svstate.dststep, 0)
 963             # when end reached, vertical mode is exited
 964             self.assertEqual(sim.svstate.vfirst, 0)
 965             CR0 = sim.crl[0]
 966             print("      CR0", bin(CR0.get_range().value))
 967             self.assertEqual(CR0[CRFields.EQ], 0)
 968             self.assertEqual(CR0[CRFields.LT], 0)
 969             self.assertEqual(CR0[CRFields.GT], 0)
 970             self.assertEqual(CR0[CRFields.SO], 1)
 971
 972             # check registers as expected
 973             self._check_regs(sim, expected_regs)
 974
 975     def test_svstep_max_idx(self):
 976         """tests svstep with a branch, get the index of the greatest element.
 977         uses sv.cmp and sv.isel as a temporary substitute for sv.max,
 978         but also uses the same trick when getting the srcstep.
 979         """
 980         lst = SVP64Asm(["setvl 0, 0, 5, 1, 1, 1",
 981                         'sv.cmp 0, 1, *4, 14',  # r8 contains the temp
 982                         'sv.isel 14,*4,14,1',  # copy if cmp was greater
 983                         "svstep. 12, 6, 0",  # get srcstep
 984                         'sv.isel 10,12,10,1',  # copy if cmp was greater
 985                         "svstep. 0, 1, 0",  # svstep (Rc=1)
 986                         "bc 6, 3, -0x24"  # branch to cmp
 987                         ])
 988         lst = list(lst)
 989
 990         # initial values in GPR regfile
 991         initial_regs = [0] * 32
 992         initial_regs[4] = 0x2
 993         initial_regs[5] = 0x1
 994         initial_regs[6] = 0x7
 995         initial_regs[7] = 0x9
 996         initial_regs[8] = 0x3
 997
 998         # copy before running
 999         expected_regs = deepcopy(initial_regs)
1000         idx = -1
1001         maxval = -1
1002         for i in range(5):
1003             if initial_regs[4+i] > maxval:
1004                 maxval = initial_regs[4+i]
1005                 idx = i
1006         expected_regs[14] = maxval  # largest number
1007         expected_regs[12] = idx     # index of largest
1008
1009         with Program(lst, bigendian=False) as program:
1010             sim = self.run_tst_program(program, initial_regs)
1011             print("SVSTATE after", bin(sim.svstate.asint()))
1012             print("        vl", bin(sim.svstate.vl))
1013             print("        mvl", bin(sim.svstate.maxvl))
1014             print("    srcstep", bin(sim.svstate.srcstep))
1015             print("    dststep", bin(sim.svstate.dststep))
1016             print("     vfirst", bin(sim.svstate. vfirst))
1017             self.assertEqual(sim.svstate.vl, 5)
1018             self.assertEqual(sim.svstate.maxvl, 5)
1019             self.assertEqual(sim.svstate.srcstep, 0)
1020             self.assertEqual(sim.svstate.dststep, 0)
1021             # when end reached, vertical mode is exited
1022             self.assertEqual(sim.svstate.vfirst, 0)
1023             CR0 = sim.crl[0]
1024             print("      CR0", bin(CR0.get_range().value))
1025             self.assertEqual(CR0[CRFields.EQ], 0)
1026             self.assertEqual(CR0[CRFields.LT], 0)
1027             self.assertEqual(CR0[CRFields.GT], 0)
1028             self.assertEqual(CR0[CRFields.SO], 1)
1029
1030             # check registers as expected
1031             self._check_regs(sim, expected_regs)
1032
1033     def test_svremap(self):
1034         """svremap, see if values get set
1035         """
1036         lst = SVP64Asm(["svremap 11, 0, 1, 2, 3, 3, 1",
1037                         ])
1038         lst = list(lst)
1039
1040         with Program(lst, bigendian=False) as program:
1041             sim = self.run_tst_program(program)
1042             svstate = sim.svstate
1043             print("SVREMAP after", bin(svstate.value))
1044             print("        men", bin(svstate.SVme))
1045             print("        mi0", bin(svstate.mi0))
1046             print("        mi1", bin(svstate.mi1))
1047             print("        mi2", bin(svstate.mi2))
1048             print("        mo0", bin(svstate.mo0))
1049             print("        mo1", bin(svstate.mo1))
1050             print("    persist", bin(svstate.RMpst))
1051             self.assertEqual(svstate.SVme, 11)
1052             self.assertEqual(svstate.mi0, 0)
1053             self.assertEqual(svstate.mi1, 1)
1054             self.assertEqual(svstate.mi2, 2)
1055             self.assertEqual(svstate.mo0, 3)
1056             self.assertEqual(svstate.mo1, 3)
1057             self.assertEqual(svstate.RMpst, 1)
1058
1059     def test_svstep_iota(self):
1060         """tests svstep "straight", placing srcstep, dststep into vector
1061         """
1062         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
1063                         "sv.svstep *0, 5, 1",  # svstep get vector srcstep
1064                         "sv.svstep. *4, 6, 1",  # svstep get vector dststep
1065                         ])
1066         lst = list(lst)
1067
1068         # SVSTATE
1069         svstate = SVP64State()
1070         # svstate.vl = 2 # VL
1071         # svstate.maxvl = 2 # MAXVL
1072         print("SVSTATE", bin(svstate.asint()))
1073
1074         with Program(lst, bigendian=False) as program:
1075             sim = self.run_tst_program(program, svstate=svstate)
1076             print("SVSTATE after", bin(sim.svstate.asint()))
1077             print("        vl", bin(sim.svstate.vl))
1078             print("        mvl", bin(sim.svstate.maxvl))
1079             print("    srcstep", bin(sim.svstate.srcstep))
1080             print("    dststep", bin(sim.svstate.dststep))
1081             print("     vfirst", bin(sim.svstate. vfirst))
1082             self.assertEqual(sim.svstate.vl, 4)
1083             self.assertEqual(sim.svstate.maxvl, 4)
1084             # svstep called four times, reset occurs, srcstep zero
1085             self.assertEqual(sim.svstate.srcstep, 0)
1086             self.assertEqual(sim.svstate.dststep, 0)
1087             for i in range(4):
1088                 self.assertEqual(sim.gpr(0+i), SelectableInt(i, 64))
1089                 self.assertEqual(sim.gpr(4+i), SelectableInt(i, 64))
1090             self.assertEqual(sim.svstate.vfirst, 0)
1091             CR0 = sim.crl[0]
1092             print("      CR0", bin(CR0.get_range().value))
1093             self.assertEqual(CR0[CRFields.EQ], 0)
1094             self.assertEqual(CR0[CRFields.LT], 0)
1095             self.assertEqual(CR0[CRFields.GT], 0)
1096             self.assertEqual(CR0[CRFields.SO], 1)
1097
1098     def test_svstep_iota_mask(self):
1099         """tests svstep "straight", placing srcstep, dststep into vector
1100         """
1101         lst = SVP64Asm(["setvl 0, 0, 5, 0, 1, 1",
1102                         "sv.svstep/m=r30 *0, 5, 1",  # svstep get vector srcstep
1103                         "sv.svstep./m=r30 *8, 6, 1",  # svstep get vector dststep
1104                         ])
1105         lst = list(lst)
1106
1107         # SVSTATE
1108         svstate = SVP64State()
1109         # svstate.vl = 2 # VL
1110         # svstate.maxvl = 2 # MAXVL
1111         print("SVSTATE", bin(svstate.asint()))
1112
1113         mask = 0b10101
1114         initial_regs = [0] * 32
1115         initial_regs[30] = mask
1116
1117         with Program(lst, bigendian=False) as program:
1118             sim = self.run_tst_program(program, svstate=svstate,
1119                                        initial_regs=initial_regs)
1120             print("SVSTATE after", bin(sim.svstate.asint()))
1121             print("        vl", bin(sim.svstate.vl))
1122             print("        mvl", bin(sim.svstate.maxvl))
1123             print("    srcstep", bin(sim.svstate.srcstep))
1124             print("    dststep", bin(sim.svstate.dststep))
1125             print("     vfirst", bin(sim.svstate. vfirst))
1126             self.assertEqual(sim.svstate.vl, 5)
1127             self.assertEqual(sim.svstate.maxvl, 5)
1128             # svstep called four times, reset occurs, srcstep zero
1129             self.assertEqual(sim.svstate.srcstep, 0)
1130             self.assertEqual(sim.svstate.dststep, 0)
1131             sim.gpr.dump()
1132             for i in range(5):
1133                 if mask & (1 << i):
1134                     tst = i
1135                 else:
1136                     tst = 0
1137                 self.assertEqual(sim.gpr(0+i), SelectableInt(tst, 64))
1138                 self.assertEqual(sim.gpr(8+i), SelectableInt(tst, 64))
1139             self.assertEqual(sim.svstate.vfirst, 0)
1140             CR4 = sim.crl[4]
1141             print("      CR4", bin(CR4.get_range().value))
1142             self.assertEqual(CR4[CRFields.EQ], 0)
1143             self.assertEqual(CR4[CRFields.LT], 0)
1144             self.assertEqual(CR4[CRFields.GT], 0)
1145             self.assertEqual(CR4[CRFields.SO], 0)
1146
1147     def run_tst_program(self, prog, initial_regs=None,
1148                         svstate=None,
1149                         initial_sprs=None):
1150         if initial_regs is None:
1151             initial_regs = [0] * 32
1152         simulator = run_tst(prog, initial_regs, svstate=svstate,
1153                             initial_sprs=initial_sprs)
1154         simulator.gpr.dump()
1155         return simulator
1156
1157
1158 if __name__ == "__main__":
1159     unittest.main()