1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
, CRFields
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
18 class DecoderTestCase(FHDLTestCase
):
20 def _check_regs(self
, sim
, expected
):
24 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
26 def test_svstep_1(self
):
27 lst
= SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode)
28 "setvl 0, 0, 1, 1, 0, 0", # svstep
29 "setvl 0, 0, 1, 1, 0, 0" # svstep
33 # SVSTATE (in this case, VL=4) which is going to get erased by setvl
34 svstate
= SVP64State()
36 svstate
.maxvl
= 4 # MAXVL
37 print ("SVSTATE", bin(svstate
.asint()))
39 with
Program(lst
, bigendian
=False) as program
:
40 sim
= self
.run_tst_program(program
, svstate
=svstate
)
41 print ("SVSTATE after", bin(sim
.svstate
.asint()))
42 print (" vl", bin(sim
.svstate
.vl
))
43 print (" mvl", bin(sim
.svstate
.maxvl
))
44 print (" srcstep", bin(sim
.svstate
.srcstep
))
45 print (" dststep", bin(sim
.svstate
.dststep
))
46 print (" vfirst", bin(sim
.svstate
.vfirst
))
47 self
.assertEqual(sim
.svstate
.vl
, 10)
48 self
.assertEqual(sim
.svstate
.maxvl
, 10)
49 self
.assertEqual(sim
.svstate
.srcstep
, 2)
50 self
.assertEqual(sim
.svstate
.dststep
, 2)
51 self
.assertEqual(sim
.svstate
.vfirst
, 1)
52 print(" gpr1", sim
.gpr(0))
53 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
55 def test_svstep_2(self
):
56 """tests svstep when it reaches VL
58 lst
= SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", # actual setvl (VF mode)
59 "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
60 "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
64 # SVSTATE (in this case, VL=2)
65 svstate
= SVP64State()
67 svstate
.maxvl
= 2 # MAXVL
68 print ("SVSTATE", bin(svstate
.asint()))
70 with
Program(lst
, bigendian
=False) as program
:
71 sim
= self
.run_tst_program(program
, svstate
=svstate
)
72 print ("SVSTATE after", bin(sim
.svstate
.asint()))
73 print (" vl", bin(sim
.svstate
.vl
))
74 print (" mvl", bin(sim
.svstate
.maxvl
))
75 print (" srcstep", bin(sim
.svstate
.srcstep
))
76 print (" dststep", bin(sim
.svstate
.dststep
))
77 print (" vfirst", bin(sim
.svstate
.vfirst
))
78 self
.assertEqual(sim
.svstate
.vl
, 2)
79 self
.assertEqual(sim
.svstate
.maxvl
, 2)
80 self
.assertEqual(sim
.svstate
.srcstep
, 0)
81 self
.assertEqual(sim
.svstate
.dststep
, 0)
82 # when end reached, vertical mode is exited
83 self
.assertEqual(sim
.svstate
.vfirst
, 0)
84 print(" gpr1", sim
.gpr(0))
85 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
87 print(" CR0", bin(CR0
.get_range().value
))
88 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
89 self
.assertEqual(CR0
[CRFields
.LT
], 0)
90 self
.assertEqual(CR0
[CRFields
.GT
], 0)
91 self
.assertEqual(CR0
[CRFields
.SO
], 1)
93 def test_svstep_3(self
):
94 """tests svstep when it *doesn't* reach VL
96 lst
= SVP64Asm(["setvl 0, 0, 3, 1, 1, 1", # actual setvl (VF mode)
97 "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
98 "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
102 # SVSTATE (in this case, VL=2)
103 svstate
= SVP64State()
105 svstate
.maxvl
= 2 # MAXVL
106 print ("SVSTATE", bin(svstate
.asint()))
108 with
Program(lst
, bigendian
=False) as program
:
109 sim
= self
.run_tst_program(program
, svstate
=svstate
)
110 print ("SVSTATE after", bin(sim
.svstate
.asint()))
111 print (" vl", bin(sim
.svstate
.vl
))
112 print (" mvl", bin(sim
.svstate
.maxvl
))
113 print (" srcstep", bin(sim
.svstate
.srcstep
))
114 print (" dststep", bin(sim
.svstate
.dststep
))
115 print (" vfirst", bin(sim
.svstate
. vfirst
))
116 self
.assertEqual(sim
.svstate
.vl
, 3)
117 self
.assertEqual(sim
.svstate
.maxvl
, 3)
118 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
119 self
.assertEqual(sim
.svstate
.srcstep
, 2)
120 self
.assertEqual(sim
.svstate
.dststep
, 2)
121 print(" gpr1", sim
.gpr(0))
122 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
123 self
.assertEqual(sim
.svstate
.vfirst
, 1)
125 print(" CR0", bin(CR0
.get_range().value
))
126 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
127 self
.assertEqual(CR0
[CRFields
.LT
], 0)
128 self
.assertEqual(CR0
[CRFields
.GT
], 0)
129 self
.assertEqual(CR0
[CRFields
.SO
], 0)
132 def test_setvl_1(self
):
133 """straight setvl, testing if VL and MVL are over-ridden
135 lst
= SVP64Asm(["setvl 1, 0, 10, 0, 1, 1",
139 # SVSTATE (in this case, VL=2), want to see if these get changed
140 svstate
= SVP64State()
142 svstate
.maxvl
= 2 # MAXVL
143 print ("SVSTATE", bin(svstate
.asint()))
145 with
Program(lst
, bigendian
=False) as program
:
146 sim
= self
.run_tst_program(program
, svstate
=svstate
)
147 print ("SVSTATE after", bin(sim
.svstate
.asint()))
148 print (" vl", bin(sim
.svstate
.vl
))
149 print (" mvl", bin(sim
.svstate
.maxvl
))
150 self
.assertEqual(sim
.svstate
.vl
, 10)
151 self
.assertEqual(sim
.svstate
.maxvl
, 10)
152 self
.assertEqual(sim
.svstate
.maxvl
, 10)
153 print(" gpr1", sim
.gpr(1))
154 self
.assertEqual(sim
.gpr(1), SelectableInt(10, 64))
156 def test_svstep_inner_loop_6(self
):
157 """tests svstep inner loop, running 6 times, looking for "k".
158 also sees if k is actually output into reg 2 (RT=2)
161 # set triple butterfly mode with persistent "REMAP"
162 "svshape 8, 1, 1, 1, 1",
163 "svremap 31, 1, 0, 2, 0, 1, 1",
164 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
165 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
166 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
167 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
168 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
169 "setvl. 2, 0, 2, 1, 0, 0",# svstep (Rc=1)
174 svstate
= SVP64State()
176 #svstate.maxvl = 2 # MAXVL
177 print ("SVSTATE", bin(svstate
.asint()))
179 with
Program(lst
, bigendian
=False) as program
:
180 sim
= self
.run_tst_program(program
, svstate
=svstate
)
181 print ("SVSTATE after", bin(sim
.svstate
.asint()))
182 print (" vl", bin(sim
.svstate
.vl
))
183 print (" mvl", bin(sim
.svstate
.maxvl
))
184 print (" srcstep", bin(sim
.svstate
.srcstep
))
185 print (" dststep", bin(sim
.svstate
.dststep
))
186 print (" vfirst", bin(sim
.svstate
. vfirst
))
187 self
.assertEqual(sim
.svstate
.vl
, 12)
188 self
.assertEqual(sim
.svstate
.maxvl
, 12)
189 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
190 self
.assertEqual(sim
.svstate
.srcstep
, 6)
191 self
.assertEqual(sim
.svstate
.dststep
, 6)
192 self
.assertEqual(sim
.gpr(2), SelectableInt(1, 64))
193 self
.assertEqual(sim
.svstate
.vfirst
, 1)
195 print(" CR0", bin(CR0
.get_range().value
))
196 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
197 self
.assertEqual(CR0
[CRFields
.LT
], 1)
198 self
.assertEqual(CR0
[CRFields
.GT
], 1)
199 self
.assertEqual(CR0
[CRFields
.SO
], 0)
201 def test_svstep_inner_loop_3(self
):
202 """tests svstep inner loop, running 3 times
205 # set triple butterfly mode with persistent "REMAP"
206 "svshape 8, 1, 1, 1, 1",
207 "svremap 31, 1, 0, 2, 0, 1, 1",
208 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
209 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
210 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
215 svstate
= SVP64State()
217 #svstate.maxvl = 2 # MAXVL
218 print ("SVSTATE", bin(svstate
.asint()))
220 with
Program(lst
, bigendian
=False) as program
:
221 sim
= self
.run_tst_program(program
, svstate
=svstate
)
222 print ("SVSTATE after", bin(sim
.svstate
.asint()))
223 print (" vl", bin(sim
.svstate
.vl
))
224 print (" mvl", bin(sim
.svstate
.maxvl
))
225 print (" srcstep", bin(sim
.svstate
.srcstep
))
226 print (" dststep", bin(sim
.svstate
.dststep
))
227 print (" vfirst", bin(sim
.svstate
. vfirst
))
228 self
.assertEqual(sim
.svstate
.vl
, 12)
229 self
.assertEqual(sim
.svstate
.maxvl
, 12)
230 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
231 self
.assertEqual(sim
.svstate
.srcstep
, 3)
232 self
.assertEqual(sim
.svstate
.dststep
, 3)
233 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
234 self
.assertEqual(sim
.svstate
.vfirst
, 1)
236 print(" CR0", bin(CR0
.get_range().value
))
237 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
238 self
.assertEqual(CR0
[CRFields
.LT
], 1)
239 self
.assertEqual(CR0
[CRFields
.GT
], 1)
240 self
.assertEqual(CR0
[CRFields
.SO
], 0)
242 def test_svstep_inner_loop_4(self
):
243 """tests svstep inner loop, running 4 times
246 # set triple butterfly mode with persistent "REMAP"
247 "svshape 8, 1, 1, 1, 1",
248 "svremap 31, 1, 0, 2, 0, 1, 1",
249 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
250 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
251 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
252 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
257 svstate
= SVP64State()
259 #svstate.maxvl = 2 # MAXVL
260 print ("SVSTATE", bin(svstate
.asint()))
262 with
Program(lst
, bigendian
=False) as program
:
263 sim
= self
.run_tst_program(program
, svstate
=svstate
)
264 print ("SVSTATE after", bin(sim
.svstate
.asint()))
265 print (" vl", bin(sim
.svstate
.vl
))
266 print (" mvl", bin(sim
.svstate
.maxvl
))
267 print (" srcstep", bin(sim
.svstate
.srcstep
))
268 print (" dststep", bin(sim
.svstate
.dststep
))
269 print (" vfirst", bin(sim
.svstate
. vfirst
))
270 self
.assertEqual(sim
.svstate
.vl
, 12)
271 self
.assertEqual(sim
.svstate
.maxvl
, 12)
272 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
273 self
.assertEqual(sim
.svstate
.srcstep
, 4)
274 self
.assertEqual(sim
.svstate
.dststep
, 4)
275 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
276 self
.assertEqual(sim
.svstate
.vfirst
, 1)
278 print(" CR0", bin(CR0
.get_range().value
))
279 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
280 self
.assertEqual(CR0
[CRFields
.LT
], 1)
281 self
.assertEqual(CR0
[CRFields
.GT
], 0)
282 self
.assertEqual(CR0
[CRFields
.SO
], 0)
284 def test_svstep_inner_loop_4_jl(self
):
285 """tests svstep inner loop, running 4 times, checking
286 "jl" is returned after 4th iteration
289 # set triple butterfly mode with persistent "REMAP"
290 "svshape 8, 1, 1, 1, 1",
291 "svremap 31, 1, 0, 2, 0, 1, 1",
292 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
293 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
294 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
295 "setvl. 2, 0, 2, 1, 0, 0", # svstep (Rc=1)
300 svstate
= SVP64State()
302 #svstate.maxvl = 2 # MAXVL
303 print ("SVSTATE", bin(svstate
.asint()))
305 with
Program(lst
, bigendian
=False) as program
:
306 sim
= self
.run_tst_program(program
, svstate
=svstate
)
307 print ("SVSTATE after", bin(sim
.svstate
.asint()))
308 print (" vl", bin(sim
.svstate
.vl
))
309 print (" mvl", bin(sim
.svstate
.maxvl
))
310 print (" srcstep", bin(sim
.svstate
.srcstep
))
311 print (" dststep", bin(sim
.svstate
.dststep
))
312 print (" vfirst", bin(sim
.svstate
. vfirst
))
313 self
.assertEqual(sim
.svstate
.vl
, 12)
314 self
.assertEqual(sim
.svstate
.maxvl
, 12)
315 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
316 self
.assertEqual(sim
.svstate
.srcstep
, 4)
317 self
.assertEqual(sim
.svstate
.dststep
, 4)
318 self
.assertEqual(sim
.gpr(2), SelectableInt(6, 64))
319 self
.assertEqual(sim
.svstate
.vfirst
, 1)
321 print(" CR0", bin(CR0
.get_range().value
))
322 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
323 self
.assertEqual(CR0
[CRFields
.LT
], 1)
324 self
.assertEqual(CR0
[CRFields
.GT
], 0)
325 self
.assertEqual(CR0
[CRFields
.SO
], 0)
327 def test_svstep_inner_loop_8_jl(self
):
328 """tests svstep inner loop, running 8 times (sv.setvl.), checking
329 jl is copied into a *Vector* result.
334 # set DCT triple butterfly mode with persistent "REMAP"
335 "svshape 8, 1, 1, 2, 0",
336 "svremap 0, 0, 0, 2, 0, 1, 1",
337 "sv.svstep 2.v, 4, 1", # svstep get vector of ci
338 "sv.svstep 16.v, 3, 1", # svstep get vector of step
343 svstate
= SVP64State()
345 #svstate.maxvl = 2 # MAXVL
346 print ("SVSTATE", bin(svstate
.asint()))
348 with
Program(lst
, bigendian
=False) as program
:
349 sim
= self
.run_tst_program(program
, svstate
=svstate
)
350 print ("SVSTATE after", bin(sim
.svstate
.asint()))
351 print (" vl", bin(sim
.svstate
.vl
))
352 print (" mvl", bin(sim
.svstate
.maxvl
))
353 print (" srcstep", bin(sim
.svstate
.srcstep
))
354 print (" dststep", bin(sim
.svstate
.dststep
))
355 print (" vfirst", bin(sim
.svstate
. vfirst
))
356 self
.assertEqual(sim
.svstate
.vl
, 12)
357 self
.assertEqual(sim
.svstate
.maxvl
, 12)
358 # svstep called four times, reset occurs, srcstep zero
359 self
.assertEqual(sim
.svstate
.srcstep
, 0)
360 self
.assertEqual(sim
.svstate
.dststep
, 0)
362 self
.assertEqual(sim
.gpr(2+i
), SelectableInt(8, 64))
363 self
.assertEqual(sim
.gpr(6+i
), SelectableInt(4, 64))
364 self
.assertEqual(sim
.gpr(10+i
), SelectableInt(2, 64))
365 self
.assertEqual(sim
.gpr(16+i
), SelectableInt(i
, 64))
366 self
.assertEqual(sim
.gpr(24+i
), SelectableInt(0, 64))
368 self
.assertEqual(sim
.gpr(20+i
), SelectableInt(i
, 64))
369 self
.assertEqual(sim
.gpr(22+i
), SelectableInt(i
, 64))
370 self
.assertEqual(sim
.svstate
.vfirst
, 0)
372 print(" CR0", bin(CR0
.get_range().value
))
373 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
374 self
.assertEqual(CR0
[CRFields
.LT
], 0)
375 self
.assertEqual(CR0
[CRFields
.GT
], 0)
376 self
.assertEqual(CR0
[CRFields
.SO
], 0)
378 def test_sv_add(self
):
379 """sets VL=2 then adds:
380 * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
381 * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
383 isa
= SVP64Asm(["setvl 3, 0, 2, 0, 1, 1",
384 'sv.add 1.v, 5.v, 9.v'
387 print ("listing", lst
)
389 # initial values in GPR regfile
390 initial_regs
= [0] * 32
391 initial_regs
[9] = 0x1234
392 initial_regs
[10] = 0x1111
393 initial_regs
[5] = 0x4321
394 initial_regs
[6] = 0x2223
396 # copy before running
397 expected_regs
= deepcopy(initial_regs
)
398 expected_regs
[1] = 0x5555
399 expected_regs
[2] = 0x3334
400 expected_regs
[3] = 2 # setvl places copy of VL here
402 with
Program(lst
, bigendian
=False) as program
:
403 sim
= self
.run_tst_program(program
, initial_regs
)
404 self
._check
_regs
(sim
, expected_regs
)
406 def test_svstep_add_1(self
):
407 """tests svstep with an add, when it reaches VL
408 lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1",
409 'sv.add 1.v, 5.v, 9.v',
410 "setvl. 0, 0, 1, 1, 0, 0",
411 'sv.add 1.v, 5.v, 9.v',
412 "setvl. 0, 0, 1, 1, 0, 0"
414 sequence is as follows:
415 * setvl sets VL=2 but also "Vertical First" mode.
417 * first add, which has srcstep/dststep = 0, does add 1,5,9
418 * svstep EXPLICITLY walks srcstep/dststep to next element
419 * second add, which now has srcstep/dststep = 1, does add 2,6,10
420 * svstep EXPLICITLY walks srcstep/dststep to next element,
421 which now equals VL. srcstep and dststep are both set to
422 zero, and MSR[SVF] is cleared.
424 lst
= SVP64Asm(["setvl 3, 0, 2, 1, 1, 1",
425 'sv.add 1.v, 5.v, 9.v',
426 "setvl. 0, 0, 1, 1, 0, 0", # svstep
427 'sv.add 1.v, 5.v, 9.v',
428 "setvl. 0, 0, 1, 1, 0, 0" # svstep
432 # SVSTATE (in this case, VL=2)
433 svstate
= SVP64State()
435 svstate
.maxvl
= 2 # MAXVL
436 print ("SVSTATE", bin(svstate
.asint()))
438 # initial values in GPR regfile
439 initial_regs
= [0] * 32
440 initial_regs
[9] = 0x1234
441 initial_regs
[10] = 0x1111
442 initial_regs
[5] = 0x4321
443 initial_regs
[6] = 0x2223
445 # copy before running
446 expected_regs
= deepcopy(initial_regs
)
447 expected_regs
[1] = 0x5555
448 expected_regs
[2] = 0x3334
449 expected_regs
[3] = 2 # setvl places copy of VL here
451 with
Program(lst
, bigendian
=False) as program
:
452 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
453 print ("SVSTATE after", bin(sim
.svstate
.asint()))
454 print (" vl", bin(sim
.svstate
.vl
))
455 print (" mvl", bin(sim
.svstate
.maxvl
))
456 print (" srcstep", bin(sim
.svstate
.srcstep
))
457 print (" dststep", bin(sim
.svstate
.dststep
))
458 print (" vfirst", bin(sim
.svstate
. vfirst
))
459 self
.assertEqual(sim
.svstate
.vl
, 2)
460 self
.assertEqual(sim
.svstate
.maxvl
, 2)
461 self
.assertEqual(sim
.svstate
.srcstep
, 0)
462 self
.assertEqual(sim
.svstate
.dststep
, 0)
463 # when end reached, vertical mode is exited
464 self
.assertEqual(sim
.svstate
.vfirst
, 0)
466 print(" CR0", bin(CR0
.get_range().value
))
467 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
468 self
.assertEqual(CR0
[CRFields
.LT
], 0)
469 self
.assertEqual(CR0
[CRFields
.GT
], 0)
470 self
.assertEqual(CR0
[CRFields
.SO
], 1)
472 # check registers as expected
473 self
._check
_regs
(sim
, expected_regs
)
475 def test_svstep_add_2(self
):
476 """tests svstep with a branch.
477 lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1",
478 'sv.add 1.v, 5.v, 9.v',
479 "setvl. 0, 0, 1, 1, 0, 0",
482 sequence is as follows:
483 * setvl sets VL=2 but also "Vertical First" mode.
485 * first time add, which has srcstep/dststep = 0, does add 1,5,9
486 * svstep EXPLICITLY walks srcstep/dststep to next element,
487 not yet met VL, so CR0.EQ is set to zero
488 * branch conditional checks bne on CR0, jumps back TWELVE bytes
489 because whilst branch is 32-bit the sv.add is 64-bit
490 * second time add, which now has srcstep/dststep = 1, does add 2,6,10
491 * svstep walks to next element, meets VL, so:
492 - srcstep and dststep set to zero
494 - MSR[SVF] is cleared
495 * branch conditional detects CR0.EQ=1 and FAILs the condition,
498 we therefore have an explicit "Vertical-First" system which can
499 have **MULTIPLE* instructions inside a loop, running each element 0
500 first, then looping back and running all element 1, then all element 2
503 lst
= SVP64Asm(["setvl 3, 0, 2, 1, 1, 1",
504 'sv.add 1.v, 5.v, 9.v',
505 "setvl. 0, 0, 1, 1, 0, 0", # svstep - this is 64-bit!
506 "bc 6, 3, -0xc" # branch to add (64-bit op so -0xc!)
510 # SVSTATE (in this case, VL=2)
511 svstate
= SVP64State()
513 svstate
.maxvl
= 2 # MAXVL
514 print ("SVSTATE", bin(svstate
.asint()))
516 # initial values in GPR regfile
517 initial_regs
= [0] * 32
518 initial_regs
[9] = 0x1234
519 initial_regs
[10] = 0x1111
520 initial_regs
[5] = 0x4321
521 initial_regs
[6] = 0x2223
523 # copy before running
524 expected_regs
= deepcopy(initial_regs
)
525 expected_regs
[1] = 0x5555
526 expected_regs
[2] = 0x3334
527 expected_regs
[3] = 2 # setvl places copy of VL here
529 with
Program(lst
, bigendian
=False) as program
:
530 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
531 print ("SVSTATE after", bin(sim
.svstate
.asint()))
532 print (" vl", bin(sim
.svstate
.vl
))
533 print (" mvl", bin(sim
.svstate
.maxvl
))
534 print (" srcstep", bin(sim
.svstate
.srcstep
))
535 print (" dststep", bin(sim
.svstate
.dststep
))
536 print (" vfirst", bin(sim
.svstate
. vfirst
))
537 self
.assertEqual(sim
.svstate
.vl
, 2)
538 self
.assertEqual(sim
.svstate
.maxvl
, 2)
539 self
.assertEqual(sim
.svstate
.srcstep
, 0)
540 self
.assertEqual(sim
.svstate
.dststep
, 0)
541 # when end reached, vertical mode is exited
542 self
.assertEqual(sim
.svstate
.vfirst
, 0)
544 print(" CR0", bin(CR0
.get_range().value
))
545 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
546 self
.assertEqual(CR0
[CRFields
.LT
], 0)
547 self
.assertEqual(CR0
[CRFields
.GT
], 0)
548 self
.assertEqual(CR0
[CRFields
.SO
], 1)
550 # check registers as expected
551 self
._check
_regs
(sim
, expected_regs
)
553 def test_svremap(self
):
554 """svremap, see if values get set
556 lst
= SVP64Asm(["svremap 11, 0, 1, 2, 3, 3, 1",
560 with
Program(lst
, bigendian
=False) as program
:
561 sim
= self
.run_tst_program(program
)
562 svstate
= sim
.svstate
563 print ("SVREMAP after", bin(svstate
.value
))
564 print (" men", bin(svstate
.SVme
))
565 print (" mi0", bin(svstate
.mi0
))
566 print (" mi1", bin(svstate
.mi1
))
567 print (" mi2", bin(svstate
.mi2
))
568 print (" mo0", bin(svstate
.mo0
))
569 print (" mo1", bin(svstate
.mo1
))
570 print (" persist", bin(svstate
.RMpst
))
571 self
.assertEqual(svstate
.SVme
, 11)
572 self
.assertEqual(svstate
.mi0
, 0)
573 self
.assertEqual(svstate
.mi1
, 1)
574 self
.assertEqual(svstate
.mi2
, 2)
575 self
.assertEqual(svstate
.mo0
, 3)
576 self
.assertEqual(svstate
.mo1
, 3)
577 self
.assertEqual(svstate
.RMpst
, 1)
579 def run_tst_program(self
, prog
, initial_regs
=None,
581 if initial_regs
is None:
582 initial_regs
= [0] * 32
583 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
)
588 if __name__
== "__main__":