src/openpower/decoder/isa/test_caller_setvl.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         print ("GPR")
  22         sim.gpr.dump()
  23         for i in range(32):
  24             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  25
  26     def test_svstep_1(self):
  27         lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode)
  28                         "setvl 0, 0, 1, 1, 0, 0", # svstep
  29                         "setvl 0, 0, 1, 1, 0, 0" # svstep
  30                         ])
  31         lst = list(lst)
  32
  33         # SVSTATE (in this case, VL=4) which is going to get erased by setvl
  34         svstate = SVP64State()
  35         svstate.vl = 4 # VL
  36         svstate.maxvl = 4 # MAXVL
  37         print ("SVSTATE", bin(svstate.asint()))
  38
  39         with Program(lst, bigendian=False) as program:
  40             sim = self.run_tst_program(program, svstate=svstate)
  41             print ("SVSTATE after", bin(sim.svstate.asint()))
  42             print ("        vl", bin(sim.svstate.vl))
  43             print ("        mvl", bin(sim.svstate.maxvl))
  44             print ("    srcstep", bin(sim.svstate.srcstep))
  45             print ("    dststep", bin(sim.svstate.dststep))
  46             print ("     vfirst", bin(sim.svstate.vfirst))
  47             self.assertEqual(sim.svstate.vl, 10)
  48             self.assertEqual(sim.svstate.maxvl, 10)
  49             self.assertEqual(sim.svstate.srcstep, 2)
  50             self.assertEqual(sim.svstate.dststep, 2)
  51             self.assertEqual(sim.svstate.vfirst, 1)
  52             print("      gpr1", sim.gpr(0))
  53             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
  54
  55     def test_svstep_2(self):
  56         """tests svstep when it reaches VL
  57         """
  58         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",  # actual setvl (VF mode)
  59                         "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
  60                         "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
  61                         ])
  62         lst = list(lst)
  63
  64         # SVSTATE (in this case, VL=2)
  65         svstate = SVP64State()
  66         svstate.vl = 2 # VL
  67         svstate.maxvl = 2 # MAXVL
  68         print ("SVSTATE", bin(svstate.asint()))
  69
  70         with Program(lst, bigendian=False) as program:
  71             sim = self.run_tst_program(program, svstate=svstate)
  72             print ("SVSTATE after", bin(sim.svstate.asint()))
  73             print ("        vl", bin(sim.svstate.vl))
  74             print ("        mvl", bin(sim.svstate.maxvl))
  75             print ("    srcstep", bin(sim.svstate.srcstep))
  76             print ("    dststep", bin(sim.svstate.dststep))
  77             print ("     vfirst", bin(sim.svstate.vfirst))
  78             self.assertEqual(sim.svstate.vl, 2)
  79             self.assertEqual(sim.svstate.maxvl, 2)
  80             self.assertEqual(sim.svstate.srcstep, 0)
  81             self.assertEqual(sim.svstate.dststep, 0)
  82             # when end reached, vertical mode is exited
  83             self.assertEqual(sim.svstate.vfirst, 0)
  84             print("      gpr1", sim.gpr(0))
  85             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
  86             CR0 = sim.crl[0]
  87             print("      CR0", bin(CR0.get_range().value))
  88             self.assertEqual(CR0[CRFields.EQ], 0)
  89             self.assertEqual(CR0[CRFields.LT], 0)
  90             self.assertEqual(CR0[CRFields.GT], 0)
  91             self.assertEqual(CR0[CRFields.SO], 1)
  92
  93     def test_svstep_3(self):
  94         """tests svstep when it *doesn't* reach VL
  95         """
  96         lst = SVP64Asm(["setvl 0, 0, 3, 1, 1, 1",  # actual setvl (VF mode)
  97                         "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
  98                         "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
  99                         ])
 100         lst = list(lst)
 101
 102         # SVSTATE (in this case, VL=2)
 103         svstate = SVP64State()
 104         svstate.vl = 2 # VL
 105         svstate.maxvl = 2 # MAXVL
 106         print ("SVSTATE", bin(svstate.asint()))
 107
 108         with Program(lst, bigendian=False) as program:
 109             sim = self.run_tst_program(program, svstate=svstate)
 110             print ("SVSTATE after", bin(sim.svstate.asint()))
 111             print ("        vl", bin(sim.svstate.vl))
 112             print ("        mvl", bin(sim.svstate.maxvl))
 113             print ("    srcstep", bin(sim.svstate.srcstep))
 114             print ("    dststep", bin(sim.svstate.dststep))
 115             print ("     vfirst", bin(sim.svstate. vfirst))
 116             self.assertEqual(sim.svstate.vl, 3)
 117             self.assertEqual(sim.svstate.maxvl, 3)
 118             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 119             self.assertEqual(sim.svstate.srcstep, 2)
 120             self.assertEqual(sim.svstate.dststep, 2)
 121             print("      gpr1", sim.gpr(0))
 122             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 123             self.assertEqual(sim.svstate.vfirst, 1)
 124             CR0 = sim.crl[0]
 125             print("      CR0", bin(CR0.get_range().value))
 126             self.assertEqual(CR0[CRFields.EQ], 0)
 127             self.assertEqual(CR0[CRFields.LT], 0)
 128             self.assertEqual(CR0[CRFields.GT], 0)
 129             self.assertEqual(CR0[CRFields.SO], 0)
 130
 131
 132     def test_setvl_1(self):
 133         """straight setvl, testing if VL and MVL are over-ridden
 134         """
 135         lst = SVP64Asm(["setvl 0, 0, 10, 0, 1, 1",
 136                         ])
 137         lst = list(lst)
 138
 139         # SVSTATE (in this case, VL=2), want to see if these get changed
 140         svstate = SVP64State()
 141         svstate.vl = 2 # VL
 142         svstate.maxvl = 2 # MAXVL
 143         print ("SVSTATE", bin(svstate.asint()))
 144
 145         with Program(lst, bigendian=False) as program:
 146             sim = self.run_tst_program(program, svstate=svstate)
 147             print ("SVSTATE after", bin(sim.svstate.asint()))
 148             print ("        vl", bin(sim.svstate.vl))
 149             print ("        mvl", bin(sim.svstate.maxvl))
 150             self.assertEqual(sim.svstate.vl, 10)
 151             self.assertEqual(sim.svstate.maxvl, 10)
 152             print("      gpr1", sim.gpr(1))
 153             self.assertEqual(sim.gpr(1), SelectableInt(0, 64))
 154
 155     def test_setvl_2(self):
 156         """setvl, testing if VL is transferred to RT, and MVL truncates it
 157         """
 158         lst = SVP64Asm(["setvl 1, 0, 2, 0, 0, 1",
 159                         ])
 160         lst = list(lst)
 161
 162         # SVSTATE (in this case, VL=2), want to see if these get changed
 163         svstate = SVP64State()
 164         svstate.vl = 10 # VL
 165         svstate.maxvl = 10 # MAXVL
 166         print ("SVSTATE", bin(svstate.asint()))
 167
 168         with Program(lst, bigendian=False) as program:
 169             sim = self.run_tst_program(program, svstate=svstate)
 170             print ("SVSTATE after", bin(sim.svstate.asint()))
 171             print ("        vl", bin(sim.svstate.vl))
 172             print ("        mvl", bin(sim.svstate.maxvl))
 173             self.assertEqual(sim.svstate.maxvl, 2)
 174             self.assertEqual(sim.svstate.vl, 2)
 175             print("      gpr1", sim.gpr(1))
 176             self.assertEqual(sim.gpr(1), SelectableInt(2, 64))
 177
 178     def test_svstep_inner_loop_6(self):
 179         """tests svstep inner loop, running 6 times, looking for "k".
 180         also sees if k is actually output into reg 2 (RT=2)
 181         """
 182         lst = SVP64Asm([
 183                         # set triple butterfly mode with persistent "REMAP"
 184                         "svshape 8, 1, 1, 1, 1",
 185                         "svremap 31, 1, 0, 2, 0, 1, 1",
 186                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 187                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 188                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 189                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 190                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 191                         "setvl. 2, 0, 2, 1, 0, 0",# svstep (Rc=1)
 192                         ])
 193         lst = list(lst)
 194
 195         # SVSTATE
 196         svstate = SVP64State()
 197         #svstate.vl = 2 # VL
 198         #svstate.maxvl = 2 # MAXVL
 199         print ("SVSTATE", bin(svstate.asint()))
 200
 201         with Program(lst, bigendian=False) as program:
 202             sim = self.run_tst_program(program, svstate=svstate)
 203             print ("SVSTATE after", bin(sim.svstate.asint()))
 204             print ("        vl", bin(sim.svstate.vl))
 205             print ("        mvl", bin(sim.svstate.maxvl))
 206             print ("    srcstep", bin(sim.svstate.srcstep))
 207             print ("    dststep", bin(sim.svstate.dststep))
 208             print ("     vfirst", bin(sim.svstate. vfirst))
 209             self.assertEqual(sim.svstate.vl, 12)
 210             self.assertEqual(sim.svstate.maxvl, 12)
 211             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 212             self.assertEqual(sim.svstate.srcstep, 6)
 213             self.assertEqual(sim.svstate.dststep, 6)
 214             self.assertEqual(sim.gpr(2), SelectableInt(1, 64))
 215             self.assertEqual(sim.svstate.vfirst, 1)
 216             CR0 = sim.crl[0]
 217             print("      CR0", bin(CR0.get_range().value))
 218             self.assertEqual(CR0[CRFields.EQ], 0)
 219             self.assertEqual(CR0[CRFields.LT], 1)
 220             self.assertEqual(CR0[CRFields.GT], 1)
 221             self.assertEqual(CR0[CRFields.SO], 0)
 222
 223     def test_svstep_inner_loop_3(self):
 224         """tests svstep inner loop, running 3 times
 225         """
 226         lst = SVP64Asm([
 227                         # set triple butterfly mode with persistent "REMAP"
 228                         "svshape 8, 1, 1, 1, 1",
 229                         "svremap 31, 1, 0, 2, 0, 1, 1",
 230                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 231                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 232                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 233                         ])
 234         lst = list(lst)
 235
 236         # SVSTATE
 237         svstate = SVP64State()
 238         #svstate.vl = 2 # VL
 239         #svstate.maxvl = 2 # MAXVL
 240         print ("SVSTATE", bin(svstate.asint()))
 241
 242         with Program(lst, bigendian=False) as program:
 243             sim = self.run_tst_program(program, svstate=svstate)
 244             print ("SVSTATE after", bin(sim.svstate.asint()))
 245             print ("        vl", bin(sim.svstate.vl))
 246             print ("        mvl", bin(sim.svstate.maxvl))
 247             print ("    srcstep", bin(sim.svstate.srcstep))
 248             print ("    dststep", bin(sim.svstate.dststep))
 249             print ("     vfirst", bin(sim.svstate. vfirst))
 250             self.assertEqual(sim.svstate.vl, 12)
 251             self.assertEqual(sim.svstate.maxvl, 12)
 252             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 253             self.assertEqual(sim.svstate.srcstep, 3)
 254             self.assertEqual(sim.svstate.dststep, 3)
 255             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 256             self.assertEqual(sim.svstate.vfirst, 1)
 257             CR0 = sim.crl[0]
 258             print("      CR0", bin(CR0.get_range().value))
 259             self.assertEqual(CR0[CRFields.EQ], 0)
 260             self.assertEqual(CR0[CRFields.LT], 1)
 261             self.assertEqual(CR0[CRFields.GT], 1)
 262             self.assertEqual(CR0[CRFields.SO], 0)
 263
 264     def test_svstep_inner_loop_4(self):
 265         """tests svstep inner loop, running 4 times
 266         """
 267         lst = SVP64Asm([
 268                         # set triple butterfly mode with persistent "REMAP"
 269                         "svshape 8, 1, 1, 1, 1",
 270                         "svremap 31, 1, 0, 2, 0, 1, 1",
 271                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 272                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 273                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 274                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 275                         ])
 276         lst = list(lst)
 277
 278         # SVSTATE
 279         svstate = SVP64State()
 280         #svstate.vl = 2 # VL
 281         #svstate.maxvl = 2 # MAXVL
 282         print ("SVSTATE", bin(svstate.asint()))
 283
 284         with Program(lst, bigendian=False) as program:
 285             sim = self.run_tst_program(program, svstate=svstate)
 286             print ("SVSTATE after", bin(sim.svstate.asint()))
 287             print ("        vl", bin(sim.svstate.vl))
 288             print ("        mvl", bin(sim.svstate.maxvl))
 289             print ("    srcstep", bin(sim.svstate.srcstep))
 290             print ("    dststep", bin(sim.svstate.dststep))
 291             print ("     vfirst", bin(sim.svstate. vfirst))
 292             self.assertEqual(sim.svstate.vl, 12)
 293             self.assertEqual(sim.svstate.maxvl, 12)
 294             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 295             self.assertEqual(sim.svstate.srcstep, 4)
 296             self.assertEqual(sim.svstate.dststep, 4)
 297             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 298             self.assertEqual(sim.svstate.vfirst, 1)
 299             CR0 = sim.crl[0]
 300             print("      CR0", bin(CR0.get_range().value))
 301             self.assertEqual(CR0[CRFields.EQ], 0)
 302             self.assertEqual(CR0[CRFields.LT], 1)
 303             self.assertEqual(CR0[CRFields.GT], 0)
 304             self.assertEqual(CR0[CRFields.SO], 0)
 305
 306     def test_svstep_inner_loop_4_jl(self):
 307         """tests svstep inner loop, running 4 times, checking
 308            "jl" is returned after 4th iteration
 309         """
 310         lst = SVP64Asm([
 311                         # set triple butterfly mode with persistent "REMAP"
 312                         "svshape 8, 1, 1, 1, 1",
 313                         "svremap 31, 1, 0, 2, 0, 1, 1",
 314                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 315                         "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
 316                         "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
 317                         "setvl. 2, 0, 2, 1, 0, 0", # svstep (Rc=1)
 318                         ])
 319         lst = list(lst)
 320
 321         # SVSTATE
 322         svstate = SVP64State()
 323         #svstate.vl = 2 # VL
 324         #svstate.maxvl = 2 # MAXVL
 325         print ("SVSTATE", bin(svstate.asint()))
 326
 327         with Program(lst, bigendian=False) as program:
 328             sim = self.run_tst_program(program, svstate=svstate)
 329             print ("SVSTATE after", bin(sim.svstate.asint()))
 330             print ("        vl", bin(sim.svstate.vl))
 331             print ("        mvl", bin(sim.svstate.maxvl))
 332             print ("    srcstep", bin(sim.svstate.srcstep))
 333             print ("    dststep", bin(sim.svstate.dststep))
 334             print ("     vfirst", bin(sim.svstate. vfirst))
 335             self.assertEqual(sim.svstate.vl, 12)
 336             self.assertEqual(sim.svstate.maxvl, 12)
 337             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 338             self.assertEqual(sim.svstate.srcstep, 4)
 339             self.assertEqual(sim.svstate.dststep, 4)
 340             self.assertEqual(sim.gpr(2), SelectableInt(6, 64))
 341             self.assertEqual(sim.svstate.vfirst, 1)
 342             CR0 = sim.crl[0]
 343             print("      CR0", bin(CR0.get_range().value))
 344             self.assertEqual(CR0[CRFields.EQ], 0)
 345             self.assertEqual(CR0[CRFields.LT], 1)
 346             self.assertEqual(CR0[CRFields.GT], 0)
 347             self.assertEqual(CR0[CRFields.SO], 0)
 348
 349     def test_svstep_inner_loop_8_jl(self):
 350         """tests svstep inner loop, running 8 times (sv.setvl.), checking
 351             jl is copied into a *Vector* result.
 352
 353             fuuun...
 354         """
 355         lst = SVP64Asm([
 356                         # set DCT triple butterfly mode with persistent "REMAP"
 357                         "svshape 8, 1, 1, 2, 0",
 358                         "svremap 0, 0, 0, 2, 0, 1, 1",
 359                         "sv.svstep 2.v, 4, 1", # svstep get vector of ci
 360                         "sv.svstep 16.v, 3, 1", # svstep get vector of step
 361                         ])
 362         lst = list(lst)
 363
 364         # SVSTATE
 365         svstate = SVP64State()
 366         #svstate.vl = 2 # VL
 367         #svstate.maxvl = 2 # MAXVL
 368         print ("SVSTATE", bin(svstate.asint()))
 369
 370         with Program(lst, bigendian=False) as program:
 371             sim = self.run_tst_program(program, svstate=svstate)
 372             print ("SVSTATE after", bin(sim.svstate.asint()))
 373             print ("        vl", bin(sim.svstate.vl))
 374             print ("        mvl", bin(sim.svstate.maxvl))
 375             print ("    srcstep", bin(sim.svstate.srcstep))
 376             print ("    dststep", bin(sim.svstate.dststep))
 377             print ("     vfirst", bin(sim.svstate. vfirst))
 378             self.assertEqual(sim.svstate.vl, 12)
 379             self.assertEqual(sim.svstate.maxvl, 12)
 380             # svstep called four times, reset occurs, srcstep zero
 381             self.assertEqual(sim.svstate.srcstep, 0)
 382             self.assertEqual(sim.svstate.dststep, 0)
 383             for i in range(4):
 384                 self.assertEqual(sim.gpr(2+i), SelectableInt(8, 64))
 385                 self.assertEqual(sim.gpr(6+i), SelectableInt(4, 64))
 386                 self.assertEqual(sim.gpr(10+i), SelectableInt(2, 64))
 387                 self.assertEqual(sim.gpr(16+i), SelectableInt(i, 64))
 388                 self.assertEqual(sim.gpr(24+i), SelectableInt(0, 64))
 389             for i in range(2):
 390                 self.assertEqual(sim.gpr(20+i), SelectableInt(i, 64))
 391                 self.assertEqual(sim.gpr(22+i), SelectableInt(i, 64))
 392             self.assertEqual(sim.svstate.vfirst, 0)
 393             CR0 = sim.crl[0]
 394             print("      CR0", bin(CR0.get_range().value))
 395             self.assertEqual(CR0[CRFields.EQ], 0)
 396             self.assertEqual(CR0[CRFields.LT], 0)
 397             self.assertEqual(CR0[CRFields.GT], 0)
 398             self.assertEqual(CR0[CRFields.SO], 0)
 399
 400     def test_sv_add(self):
 401         """sets VL=2 then adds:
 402            * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 403            * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 404         """
 405         isa = SVP64Asm(["setvl 0, 0, 2, 0, 1, 1",
 406                         'sv.add 1.v, 5.v, 9.v',
 407                         "setvl 3, 0, 0, 0, 0, 0",
 408                        ])
 409         lst = list(isa)
 410         print ("listing", lst)
 411
 412         # initial values in GPR regfile
 413         initial_regs = [0] * 32
 414         initial_regs[9] = 0x1234
 415         initial_regs[10] = 0x1111
 416         initial_regs[5] = 0x4321
 417         initial_regs[6] = 0x2223
 418
 419         # copy before running
 420         expected_regs = deepcopy(initial_regs)
 421         expected_regs[1] = 0x5555
 422         expected_regs[2] = 0x3334
 423         expected_regs[3] = 2       # setvl places copy of VL here
 424
 425         with Program(lst, bigendian=False) as program:
 426             sim = self.run_tst_program(program, initial_regs)
 427             self._check_regs(sim, expected_regs)
 428
 429     def test_svstep_add_1(self):
 430         """tests svstep with an add, when it reaches VL
 431         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 432                         'sv.add 1.v, 5.v, 9.v',
 433                         "setvl. 0, 0, 1, 1, 0, 0",
 434                         'sv.add 1.v, 5.v, 9.v',
 435                         "setvl. 3, 0, 1, 1, 0, 0"
 436                         ])
 437         sequence is as follows:
 438         * setvl sets VL=2 but also "Vertical First" mode.
 439           this sets SVSTATE[SVF].
 440         * first add, which has srcstep/dststep = 0, does add 1,5,9
 441         * svstep EXPLICITLY walks srcstep/dststep to next element
 442         * second add, which now has srcstep/dststep = 1, does add 2,6,10
 443         * svstep EXPLICITLY walks srcstep/dststep to next element,
 444           which now equals VL.  srcstep and dststep are both set to
 445           zero
 446         """
 447         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 448                         'sv.add 1.v, 5.v, 9.v',
 449                         "setvl. 0, 0, 1, 1, 0, 0",  # svstep
 450                         'sv.add 1.v, 5.v, 9.v',
 451                         "setvl. 3, 0, 1, 1, 0, 0", # svstep
 452                         "setvl 4, 0, 0, 0, 0, 0"  # svstep
 453                         ])
 454         lst = list(lst)
 455
 456         # SVSTATE (in this case, VL=2)
 457         svstate = SVP64State()
 458         svstate.vl = 2 # VL
 459         svstate.maxvl = 2 # MAXVL
 460         print ("SVSTATE", bin(svstate.asint()))
 461
 462         # initial values in GPR regfile
 463         initial_regs = [0] * 32
 464         initial_regs[9] = 0x1234
 465         initial_regs[10] = 0x1111
 466         initial_regs[5] = 0x4321
 467         initial_regs[6] = 0x2223
 468
 469         # copy before running
 470         expected_regs = deepcopy(initial_regs)
 471         expected_regs[1] = 0x5555
 472         expected_regs[2] = 0x3334
 473         expected_regs[4] = 2       # setvl places copy of VL here
 474
 475         with Program(lst, bigendian=False) as program:
 476             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 477             print ("SVSTATE after", bin(sim.svstate.asint()))
 478             print ("        vl", bin(sim.svstate.vl))
 479             print ("        mvl", bin(sim.svstate.maxvl))
 480             print ("    srcstep", bin(sim.svstate.srcstep))
 481             print ("    dststep", bin(sim.svstate.dststep))
 482             print ("     vfirst", bin(sim.svstate. vfirst))
 483             self.assertEqual(sim.svstate.vl, 2)
 484             self.assertEqual(sim.svstate.maxvl, 2)
 485             self.assertEqual(sim.svstate.srcstep, 0)
 486             self.assertEqual(sim.svstate.dststep, 0)
 487             # when end reached, vertical mode is exited
 488             self.assertEqual(sim.svstate.vfirst, 0)
 489             CR0 = sim.crl[0]
 490             print("      CR0", bin(CR0.get_range().value))
 491             self.assertEqual(CR0[CRFields.EQ], 0)
 492             self.assertEqual(CR0[CRFields.LT], 0)
 493             self.assertEqual(CR0[CRFields.GT], 0)
 494             self.assertEqual(CR0[CRFields.SO], 1)
 495
 496             # check registers as expected
 497             self._check_regs(sim, expected_regs)
 498
 499     def test_svstep_add_2(self):
 500         """tests svstep with a branch.
 501         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 502                         'sv.add 1.v, 5.v, 9.v',
 503                         "setvl. 0, 0, 1, 1, 0, 0",
 504                         "bc 6, 3, -0xc"
 505                         ])
 506         sequence is as follows:
 507         * setvl sets VL=2 but also "Vertical First" mode.
 508           this sets MSR[SVF].
 509         * first time add, which has srcstep/dststep = 0, does add 1,5,9
 510         * svstep EXPLICITLY walks srcstep/dststep to next element,
 511           not yet met VL, so CR0.EQ is set to zero
 512         * branch conditional checks bne on CR0, jumps back TWELVE bytes
 513           because whilst branch is 32-bit the sv.add is 64-bit
 514         * second time add, which now has srcstep/dststep = 1, does add 2,6,10
 515         * svstep walks to next element, meets VL, so:
 516           - srcstep and dststep set to zero
 517           - CR0.EQ set to one
 518           - MSR[SVF] is cleared
 519         * branch conditional detects CR0.EQ=1 and FAILs the condition,
 520           therefore loop ends.
 521
 522         we therefore have an explicit "Vertical-First" system which can
 523         have **MULTIPLE* instructions inside a loop, running each element 0
 524         first, then looping back and running all element 1, then all element 2
 525         etc.
 526         """
 527         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 528                         'sv.add 1.v, 5.v, 9.v',
 529                         "setvl. 0, 0, 1, 1, 0, 0", # svstep - this is 64-bit!
 530                         "bc 6, 3, -0xc" # branch to add (64-bit op so -0xc!)
 531                         ])
 532         lst = list(lst)
 533
 534         # SVSTATE (in this case, VL=2)
 535         svstate = SVP64State()
 536         svstate.vl = 2 # VL
 537         svstate.maxvl = 2 # MAXVL
 538         print ("SVSTATE", bin(svstate.asint()))
 539
 540         # initial values in GPR regfile
 541         initial_regs = [0] * 32
 542         initial_regs[9] = 0x1234
 543         initial_regs[10] = 0x1111
 544         initial_regs[5] = 0x4321
 545         initial_regs[6] = 0x2223
 546
 547         # copy before running
 548         expected_regs = deepcopy(initial_regs)
 549         expected_regs[1] = 0x5555
 550         expected_regs[2] = 0x3334
 551
 552         with Program(lst, bigendian=False) as program:
 553             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 554             print ("SVSTATE after", bin(sim.svstate.asint()))
 555             print ("        vl", bin(sim.svstate.vl))
 556             print ("        mvl", bin(sim.svstate.maxvl))
 557             print ("    srcstep", bin(sim.svstate.srcstep))
 558             print ("    dststep", bin(sim.svstate.dststep))
 559             print ("     vfirst", bin(sim.svstate. vfirst))
 560             self.assertEqual(sim.svstate.vl, 2)
 561             self.assertEqual(sim.svstate.maxvl, 2)
 562             self.assertEqual(sim.svstate.srcstep, 0)
 563             self.assertEqual(sim.svstate.dststep, 0)
 564             # when end reached, vertical mode is exited
 565             self.assertEqual(sim.svstate.vfirst, 0)
 566             CR0 = sim.crl[0]
 567             print("      CR0", bin(CR0.get_range().value))
 568             self.assertEqual(CR0[CRFields.EQ], 0)
 569             self.assertEqual(CR0[CRFields.LT], 0)
 570             self.assertEqual(CR0[CRFields.GT], 0)
 571             self.assertEqual(CR0[CRFields.SO], 1)
 572
 573             # check registers as expected
 574             self._check_regs(sim, expected_regs)
 575
 576     def test_svremap(self):
 577         """svremap, see if values get set
 578         """
 579         lst = SVP64Asm(["svremap 11, 0, 1, 2, 3, 3, 1",
 580                         ])
 581         lst = list(lst)
 582
 583         with Program(lst, bigendian=False) as program:
 584             sim = self.run_tst_program(program)
 585             svstate = sim.svstate
 586             print ("SVREMAP after", bin(svstate.value))
 587             print ("        men", bin(svstate.SVme))
 588             print ("        mi0", bin(svstate.mi0))
 589             print ("        mi1", bin(svstate.mi1))
 590             print ("        mi2", bin(svstate.mi2))
 591             print ("        mo0", bin(svstate.mo0))
 592             print ("        mo1", bin(svstate.mo1))
 593             print ("    persist", bin(svstate.RMpst))
 594             self.assertEqual(svstate.SVme, 11)
 595             self.assertEqual(svstate.mi0, 0)
 596             self.assertEqual(svstate.mi1, 1)
 597             self.assertEqual(svstate.mi2, 2)
 598             self.assertEqual(svstate.mo0, 3)
 599             self.assertEqual(svstate.mo1, 3)
 600             self.assertEqual(svstate.RMpst, 1)
 601
 602     def test_svstep_iota(self):
 603         """tests svstep "straight", placing srcstep, dststep into vector
 604         """
 605         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
 606                         "sv.svstep 0.v, 5, 1", # svstep get vector srcstep
 607                         "sv.svstep. 4.v, 6, 1", # svstep get vector dststep
 608                         ])
 609         lst = list(lst)
 610
 611         # SVSTATE
 612         svstate = SVP64State()
 613         #svstate.vl = 2 # VL
 614         #svstate.maxvl = 2 # MAXVL
 615         print ("SVSTATE", bin(svstate.asint()))
 616
 617         with Program(lst, bigendian=False) as program:
 618             sim = self.run_tst_program(program, svstate=svstate)
 619             print ("SVSTATE after", bin(sim.svstate.asint()))
 620             print ("        vl", bin(sim.svstate.vl))
 621             print ("        mvl", bin(sim.svstate.maxvl))
 622             print ("    srcstep", bin(sim.svstate.srcstep))
 623             print ("    dststep", bin(sim.svstate.dststep))
 624             print ("     vfirst", bin(sim.svstate. vfirst))
 625             self.assertEqual(sim.svstate.vl, 4)
 626             self.assertEqual(sim.svstate.maxvl, 4)
 627             # svstep called four times, reset occurs, srcstep zero
 628             self.assertEqual(sim.svstate.srcstep, 0)
 629             self.assertEqual(sim.svstate.dststep, 0)
 630             for i in range(4):
 631                 self.assertEqual(sim.gpr(0+i), SelectableInt(i, 64))
 632                 self.assertEqual(sim.gpr(4+i), SelectableInt(i, 64))
 633             self.assertEqual(sim.svstate.vfirst, 0)
 634             CR0 = sim.crl[0]
 635             print("      CR0", bin(CR0.get_range().value))
 636             self.assertEqual(CR0[CRFields.EQ], 0)
 637             self.assertEqual(CR0[CRFields.LT], 0)
 638             self.assertEqual(CR0[CRFields.GT], 0)
 639             self.assertEqual(CR0[CRFields.SO], 1)
 640
 641     def test_svstep_iota_mask(self):
 642         """tests svstep "straight", placing srcstep, dststep into vector
 643         """
 644         lst = SVP64Asm(["setvl 0, 0, 5, 0, 1, 1",
 645                         "sv.svstep/m=r30 0.v, 5, 1", # svstep get vector srcstep
 646                         "sv.svstep./m=r30 8.v, 6, 1", # svstep get vector dststep
 647                         ])
 648         lst = list(lst)
 649
 650         # SVSTATE
 651         svstate = SVP64State()
 652         #svstate.vl = 2 # VL
 653         #svstate.maxvl = 2 # MAXVL
 654         print ("SVSTATE", bin(svstate.asint()))
 655
 656         mask = 0b10101
 657         initial_regs = [0] * 32
 658         initial_regs[30] = mask
 659
 660         with Program(lst, bigendian=False) as program:
 661             sim = self.run_tst_program(program, svstate=svstate,
 662                                        initial_regs=initial_regs)
 663             print ("SVSTATE after", bin(sim.svstate.asint()))
 664             print ("        vl", bin(sim.svstate.vl))
 665             print ("        mvl", bin(sim.svstate.maxvl))
 666             print ("    srcstep", bin(sim.svstate.srcstep))
 667             print ("    dststep", bin(sim.svstate.dststep))
 668             print ("     vfirst", bin(sim.svstate. vfirst))
 669             self.assertEqual(sim.svstate.vl, 5)
 670             self.assertEqual(sim.svstate.maxvl, 5)
 671             # svstep called four times, reset occurs, srcstep zero
 672             self.assertEqual(sim.svstate.srcstep, 0)
 673             self.assertEqual(sim.svstate.dststep, 0)
 674             sim.gpr.dump()
 675             for i in range(5):
 676                 if mask & (1<<i):
 677                     tst = i
 678                 else:
 679                     tst = 0
 680                 self.assertEqual(sim.gpr(0+i), SelectableInt(tst, 64))
 681                 self.assertEqual(sim.gpr(8+i), SelectableInt(tst, 64))
 682             self.assertEqual(sim.svstate.vfirst, 0)
 683             CR4 = sim.crl[4]
 684             print("      CR4", bin(CR4.get_range().value))
 685             self.assertEqual(CR4[CRFields.EQ], 0)
 686             self.assertEqual(CR4[CRFields.LT], 0)
 687             self.assertEqual(CR4[CRFields.GT], 0)
 688             self.assertEqual(CR4[CRFields.SO], 0)
 689
 690     def run_tst_program(self, prog, initial_regs=None,
 691                               svstate=None):
 692         if initial_regs is None:
 693             initial_regs = [0] * 32
 694         simulator = run_tst(prog, initial_regs, svstate=svstate)
 695         simulator.gpr.dump()
 696         return simulator
 697
 698
 699 if __name__ == "__main__":
 700     unittest.main()
 701