1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
, CRFields
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
18 class DecoderTestCase(FHDLTestCase
):
20 def _check_regs(self
, sim
, expected
):
24 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
26 def test_svstep_1(self
):
27 lst
= SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode)
28 "setvl 0, 0, 1, 1, 0, 0", # svstep
29 "setvl 0, 0, 1, 1, 0, 0" # svstep
33 # SVSTATE (in this case, VL=4) which is going to get erased by setvl
34 svstate
= SVP64State()
36 svstate
.maxvl
= 4 # MAXVL
37 print ("SVSTATE", bin(svstate
.asint()))
39 with
Program(lst
, bigendian
=False) as program
:
40 sim
= self
.run_tst_program(program
, svstate
=svstate
)
41 print ("SVSTATE after", bin(sim
.svstate
.asint()))
42 print (" vl", bin(sim
.svstate
.vl
))
43 print (" mvl", bin(sim
.svstate
.maxvl
))
44 print (" srcstep", bin(sim
.svstate
.srcstep
))
45 print (" dststep", bin(sim
.svstate
.dststep
))
46 print (" vfirst", bin(sim
.svstate
.vfirst
))
47 self
.assertEqual(sim
.svstate
.vl
, 10)
48 self
.assertEqual(sim
.svstate
.maxvl
, 10)
49 self
.assertEqual(sim
.svstate
.srcstep
, 2)
50 self
.assertEqual(sim
.svstate
.dststep
, 2)
51 self
.assertEqual(sim
.svstate
.vfirst
, 1)
52 print(" gpr1", sim
.gpr(0))
53 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
55 def test_svstep_2(self
):
56 """tests svstep when it reaches VL
58 lst
= SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", # actual setvl (VF mode)
59 "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
60 "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
64 # SVSTATE (in this case, VL=2)
65 svstate
= SVP64State()
67 svstate
.maxvl
= 2 # MAXVL
68 print ("SVSTATE", bin(svstate
.asint()))
70 with
Program(lst
, bigendian
=False) as program
:
71 sim
= self
.run_tst_program(program
, svstate
=svstate
)
72 print ("SVSTATE after", bin(sim
.svstate
.asint()))
73 print (" vl", bin(sim
.svstate
.vl
))
74 print (" mvl", bin(sim
.svstate
.maxvl
))
75 print (" srcstep", bin(sim
.svstate
.srcstep
))
76 print (" dststep", bin(sim
.svstate
.dststep
))
77 print (" vfirst", bin(sim
.svstate
.vfirst
))
78 self
.assertEqual(sim
.svstate
.vl
, 2)
79 self
.assertEqual(sim
.svstate
.maxvl
, 2)
80 self
.assertEqual(sim
.svstate
.srcstep
, 0)
81 self
.assertEqual(sim
.svstate
.dststep
, 0)
82 # when end reached, vertical mode is exited
83 self
.assertEqual(sim
.svstate
.vfirst
, 0)
84 print(" gpr1", sim
.gpr(0))
85 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
87 print(" CR0", bin(CR0
.get_range().value
))
88 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
89 self
.assertEqual(CR0
[CRFields
.LT
], 0)
90 self
.assertEqual(CR0
[CRFields
.GT
], 0)
91 self
.assertEqual(CR0
[CRFields
.SO
], 1)
93 def test_svstep_3(self
):
94 """tests svstep when it *doesn't* reach VL
96 lst
= SVP64Asm(["setvl 0, 0, 3, 1, 1, 1", # actual setvl (VF mode)
97 "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1)
98 "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1)
102 # SVSTATE (in this case, VL=2)
103 svstate
= SVP64State()
105 svstate
.maxvl
= 2 # MAXVL
106 print ("SVSTATE", bin(svstate
.asint()))
108 with
Program(lst
, bigendian
=False) as program
:
109 sim
= self
.run_tst_program(program
, svstate
=svstate
)
110 print ("SVSTATE after", bin(sim
.svstate
.asint()))
111 print (" vl", bin(sim
.svstate
.vl
))
112 print (" mvl", bin(sim
.svstate
.maxvl
))
113 print (" srcstep", bin(sim
.svstate
.srcstep
))
114 print (" dststep", bin(sim
.svstate
.dststep
))
115 print (" vfirst", bin(sim
.svstate
. vfirst
))
116 self
.assertEqual(sim
.svstate
.vl
, 3)
117 self
.assertEqual(sim
.svstate
.maxvl
, 3)
118 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
119 self
.assertEqual(sim
.svstate
.srcstep
, 2)
120 self
.assertEqual(sim
.svstate
.dststep
, 2)
121 print(" gpr1", sim
.gpr(0))
122 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
123 self
.assertEqual(sim
.svstate
.vfirst
, 1)
125 print(" CR0", bin(CR0
.get_range().value
))
126 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
127 self
.assertEqual(CR0
[CRFields
.LT
], 0)
128 self
.assertEqual(CR0
[CRFields
.GT
], 0)
129 self
.assertEqual(CR0
[CRFields
.SO
], 0)
131 def test_setvl_ctr_1(self
):
132 """setvl CTR mode, testing if VL and MVL are over-ridden
134 lst
= SVP64Asm(["setvl 1, 0, 10, 0, 1, 1",
138 # SVSTATE (in this case, VL=2), want to see if these get changed
139 svstate
= SVP64State()
141 svstate
.maxvl
= 2 # MAXVL
142 print ("SVSTATE", bin(svstate
.asint()))
146 with
Program(lst
, bigendian
=False) as program
:
147 sim
= self
.run_tst_program(program
, svstate
=svstate
,
149 print ("SVSTATE after", bin(sim
.svstate
.asint()))
150 print (" vl", bin(sim
.svstate
.vl
))
151 print (" mvl", bin(sim
.svstate
.maxvl
))
152 self
.assertEqual(sim
.svstate
.vl
, 5)
153 self
.assertEqual(sim
.svstate
.maxvl
, 10)
154 print(" gpr1", sim
.gpr(1))
155 self
.assertEqual(sim
.gpr(1), SelectableInt(5, 64))
157 def test_setvl_ctr_2(self
):
158 """setvl CTR large, testing if VL and MVL are over-ridden
160 lst
= SVP64Asm(["setvl 1, 0, 10, 0, 1, 1",
164 # SVSTATE (in this case, VL=2), want to see if these get changed
165 svstate
= SVP64State()
167 svstate
.maxvl
= 2 # MAXVL
168 print ("SVSTATE", bin(svstate
.asint()))
169 sprs
= {'CTR': 0x1000000000,
172 with
Program(lst
, bigendian
=False) as program
:
173 sim
= self
.run_tst_program(program
, svstate
=svstate
,
175 print ("SVSTATE after", bin(sim
.svstate
.asint()))
176 print (" vl", bin(sim
.svstate
.vl
))
177 print (" mvl", bin(sim
.svstate
.maxvl
))
178 self
.assertEqual(sim
.svstate
.vl
, 10)
179 self
.assertEqual(sim
.svstate
.maxvl
, 10)
180 print(" gpr1", sim
.gpr(1))
181 self
.assertEqual(sim
.gpr(1), SelectableInt(10, 64))
183 def test_setvl_1(self
):
184 """straight setvl, testing if VL and MVL are over-ridden
186 lst
= SVP64Asm(["setvl 0, 0, 10, 0, 1, 1",
190 # SVSTATE (in this case, VL=2), want to see if these get changed
191 svstate
= SVP64State()
193 svstate
.maxvl
= 2 # MAXVL
194 print ("SVSTATE", bin(svstate
.asint()))
196 with
Program(lst
, bigendian
=False) as program
:
197 sim
= self
.run_tst_program(program
, svstate
=svstate
)
198 print ("SVSTATE after", bin(sim
.svstate
.asint()))
199 print (" vl", bin(sim
.svstate
.vl
))
200 print (" mvl", bin(sim
.svstate
.maxvl
))
201 self
.assertEqual(sim
.svstate
.vl
, 10)
202 self
.assertEqual(sim
.svstate
.maxvl
, 10)
203 print(" gpr1", sim
.gpr(1))
204 self
.assertEqual(sim
.gpr(1), SelectableInt(0, 64))
206 def test_setvl_2(self
):
207 """setvl, testing if VL is transferred to RT, and MVL truncates it
209 lst
= SVP64Asm(["setvl 1, 0, 2, 0, 0, 1",
213 # SVSTATE (in this case, VL=2), want to see if these get changed
214 svstate
= SVP64State()
216 svstate
.maxvl
= 10 # MAXVL
217 print ("SVSTATE", bin(svstate
.asint()))
219 with
Program(lst
, bigendian
=False) as program
:
220 sim
= self
.run_tst_program(program
, svstate
=svstate
)
221 print ("SVSTATE after", bin(sim
.svstate
.asint()))
222 print (" vl", bin(sim
.svstate
.vl
))
223 print (" mvl", bin(sim
.svstate
.maxvl
))
224 self
.assertEqual(sim
.svstate
.maxvl
, 2)
225 self
.assertEqual(sim
.svstate
.vl
, 2)
226 print(" gpr1", sim
.gpr(1))
227 self
.assertEqual(sim
.gpr(1), SelectableInt(2, 64))
229 def test_svstep_inner_loop_6(self
):
230 """tests svstep inner loop, running 6 times, looking for "k".
231 also sees if k is actually output into reg 2 (RT=2)
234 # set triple butterfly mode with persistent "REMAP"
235 "svshape 8, 1, 1, 1, 1",
236 "svremap 31, 1, 0, 2, 0, 1, 1",
237 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
238 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
239 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
240 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
241 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
242 "setvl. 2, 0, 2, 1, 0, 0",# svstep (Rc=1)
247 svstate
= SVP64State()
249 #svstate.maxvl = 2 # MAXVL
250 print ("SVSTATE", bin(svstate
.asint()))
252 with
Program(lst
, bigendian
=False) as program
:
253 sim
= self
.run_tst_program(program
, svstate
=svstate
)
254 print ("SVSTATE after", bin(sim
.svstate
.asint()))
255 print (" vl", bin(sim
.svstate
.vl
))
256 print (" mvl", bin(sim
.svstate
.maxvl
))
257 print (" srcstep", bin(sim
.svstate
.srcstep
))
258 print (" dststep", bin(sim
.svstate
.dststep
))
259 print (" vfirst", bin(sim
.svstate
. vfirst
))
260 self
.assertEqual(sim
.svstate
.vl
, 12)
261 self
.assertEqual(sim
.svstate
.maxvl
, 12)
262 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
263 self
.assertEqual(sim
.svstate
.srcstep
, 6)
264 self
.assertEqual(sim
.svstate
.dststep
, 6)
265 self
.assertEqual(sim
.gpr(2), SelectableInt(1, 64))
266 self
.assertEqual(sim
.svstate
.vfirst
, 1)
268 print(" CR0", bin(CR0
.get_range().value
))
269 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
270 self
.assertEqual(CR0
[CRFields
.LT
], 1)
271 self
.assertEqual(CR0
[CRFields
.GT
], 1)
272 self
.assertEqual(CR0
[CRFields
.SO
], 0)
274 def test_svstep_inner_loop_3(self
):
275 """tests svstep inner loop, running 3 times
278 # set triple butterfly mode with persistent "REMAP"
279 "svshape 8, 1, 1, 1, 1",
280 "svremap 31, 1, 0, 2, 0, 1, 1",
281 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
282 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
283 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
288 svstate
= SVP64State()
290 #svstate.maxvl = 2 # MAXVL
291 print ("SVSTATE", bin(svstate
.asint()))
293 with
Program(lst
, bigendian
=False) as program
:
294 sim
= self
.run_tst_program(program
, svstate
=svstate
)
295 print ("SVSTATE after", bin(sim
.svstate
.asint()))
296 print (" vl", bin(sim
.svstate
.vl
))
297 print (" mvl", bin(sim
.svstate
.maxvl
))
298 print (" srcstep", bin(sim
.svstate
.srcstep
))
299 print (" dststep", bin(sim
.svstate
.dststep
))
300 print (" vfirst", bin(sim
.svstate
. vfirst
))
301 self
.assertEqual(sim
.svstate
.vl
, 12)
302 self
.assertEqual(sim
.svstate
.maxvl
, 12)
303 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
304 self
.assertEqual(sim
.svstate
.srcstep
, 3)
305 self
.assertEqual(sim
.svstate
.dststep
, 3)
306 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
307 self
.assertEqual(sim
.svstate
.vfirst
, 1)
309 print(" CR0", bin(CR0
.get_range().value
))
310 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
311 self
.assertEqual(CR0
[CRFields
.LT
], 1)
312 self
.assertEqual(CR0
[CRFields
.GT
], 1)
313 self
.assertEqual(CR0
[CRFields
.SO
], 0)
315 def test_svstep_inner_loop_4(self
):
316 """tests svstep inner loop, running 4 times
319 # set triple butterfly mode with persistent "REMAP"
320 "svshape 8, 1, 1, 1, 1",
321 "svremap 31, 1, 0, 2, 0, 1, 1",
322 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
323 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
324 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
325 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
330 svstate
= SVP64State()
332 #svstate.maxvl = 2 # MAXVL
333 print ("SVSTATE", bin(svstate
.asint()))
335 with
Program(lst
, bigendian
=False) as program
:
336 sim
= self
.run_tst_program(program
, svstate
=svstate
)
337 print ("SVSTATE after", bin(sim
.svstate
.asint()))
338 print (" vl", bin(sim
.svstate
.vl
))
339 print (" mvl", bin(sim
.svstate
.maxvl
))
340 print (" srcstep", bin(sim
.svstate
.srcstep
))
341 print (" dststep", bin(sim
.svstate
.dststep
))
342 print (" vfirst", bin(sim
.svstate
. vfirst
))
343 self
.assertEqual(sim
.svstate
.vl
, 12)
344 self
.assertEqual(sim
.svstate
.maxvl
, 12)
345 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
346 self
.assertEqual(sim
.svstate
.srcstep
, 4)
347 self
.assertEqual(sim
.svstate
.dststep
, 4)
348 self
.assertEqual(sim
.gpr(0), SelectableInt(0, 64))
349 self
.assertEqual(sim
.svstate
.vfirst
, 1)
351 print(" CR0", bin(CR0
.get_range().value
))
352 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
353 self
.assertEqual(CR0
[CRFields
.LT
], 1)
354 self
.assertEqual(CR0
[CRFields
.GT
], 0)
355 self
.assertEqual(CR0
[CRFields
.SO
], 0)
357 def test_svstep_inner_loop_4_jl(self
):
358 """tests svstep inner loop, running 4 times, checking
359 "jl" is returned after 4th iteration
362 # set triple butterfly mode with persistent "REMAP"
363 "svshape 8, 1, 1, 1, 1",
364 "svremap 31, 1, 0, 2, 0, 1, 1",
365 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
366 "setvl. 0, 0, 2, 1, 0, 0",# svstep (Rc=1)
367 "setvl. 0, 0, 2, 1, 0, 0", # svstep (Rc=1)
368 "setvl. 2, 0, 2, 1, 0, 0", # svstep (Rc=1)
373 svstate
= SVP64State()
375 #svstate.maxvl = 2 # MAXVL
376 print ("SVSTATE", bin(svstate
.asint()))
378 with
Program(lst
, bigendian
=False) as program
:
379 sim
= self
.run_tst_program(program
, svstate
=svstate
)
380 print ("SVSTATE after", bin(sim
.svstate
.asint()))
381 print (" vl", bin(sim
.svstate
.vl
))
382 print (" mvl", bin(sim
.svstate
.maxvl
))
383 print (" srcstep", bin(sim
.svstate
.srcstep
))
384 print (" dststep", bin(sim
.svstate
.dststep
))
385 print (" vfirst", bin(sim
.svstate
. vfirst
))
386 self
.assertEqual(sim
.svstate
.vl
, 12)
387 self
.assertEqual(sim
.svstate
.maxvl
, 12)
388 # svstep called twice, didn't reach VL, so srcstep/dststep both 2
389 self
.assertEqual(sim
.svstate
.srcstep
, 4)
390 self
.assertEqual(sim
.svstate
.dststep
, 4)
391 self
.assertEqual(sim
.gpr(2), SelectableInt(6, 64))
392 self
.assertEqual(sim
.svstate
.vfirst
, 1)
394 print(" CR0", bin(CR0
.get_range().value
))
395 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
396 self
.assertEqual(CR0
[CRFields
.LT
], 1)
397 self
.assertEqual(CR0
[CRFields
.GT
], 0)
398 self
.assertEqual(CR0
[CRFields
.SO
], 0)
400 def test_svstep_inner_loop_8_jl(self
):
401 """tests svstep inner loop, running 8 times (sv.setvl.), checking
402 jl is copied into a *Vector* result.
407 # set DCT triple butterfly mode with persistent "REMAP"
408 "svshape 8, 1, 1, 2, 0",
409 "svremap 0, 0, 0, 2, 0, 1, 1",
410 "sv.svstep 2.v, 4, 1", # svstep get vector of ci
411 "sv.svstep 16.v, 3, 1", # svstep get vector of step
416 svstate
= SVP64State()
418 #svstate.maxvl = 2 # MAXVL
419 print ("SVSTATE", bin(svstate
.asint()))
421 with
Program(lst
, bigendian
=False) as program
:
422 sim
= self
.run_tst_program(program
, svstate
=svstate
)
423 print ("SVSTATE after", bin(sim
.svstate
.asint()))
424 print (" vl", bin(sim
.svstate
.vl
))
425 print (" mvl", bin(sim
.svstate
.maxvl
))
426 print (" srcstep", bin(sim
.svstate
.srcstep
))
427 print (" dststep", bin(sim
.svstate
.dststep
))
428 print (" vfirst", bin(sim
.svstate
. vfirst
))
429 self
.assertEqual(sim
.svstate
.vl
, 12)
430 self
.assertEqual(sim
.svstate
.maxvl
, 12)
431 # svstep called four times, reset occurs, srcstep zero
432 self
.assertEqual(sim
.svstate
.srcstep
, 0)
433 self
.assertEqual(sim
.svstate
.dststep
, 0)
435 self
.assertEqual(sim
.gpr(2+i
), SelectableInt(8, 64))
436 self
.assertEqual(sim
.gpr(6+i
), SelectableInt(4, 64))
437 self
.assertEqual(sim
.gpr(10+i
), SelectableInt(2, 64))
438 self
.assertEqual(sim
.gpr(16+i
), SelectableInt(i
, 64))
439 self
.assertEqual(sim
.gpr(24+i
), SelectableInt(0, 64))
441 self
.assertEqual(sim
.gpr(20+i
), SelectableInt(i
, 64))
442 self
.assertEqual(sim
.gpr(22+i
), SelectableInt(i
, 64))
443 self
.assertEqual(sim
.svstate
.vfirst
, 0)
445 print(" CR0", bin(CR0
.get_range().value
))
446 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
447 self
.assertEqual(CR0
[CRFields
.LT
], 0)
448 self
.assertEqual(CR0
[CRFields
.GT
], 0)
449 self
.assertEqual(CR0
[CRFields
.SO
], 0)
451 def test_sv_add(self
):
452 """sets VL=2 then adds:
453 * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
454 * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
456 isa
= SVP64Asm(["setvl 0, 0, 2, 0, 1, 1",
457 'sv.add 1.v, 5.v, 9.v',
458 "setvl 3, 0, 0, 0, 0, 0",
461 print ("listing", lst
)
463 # initial values in GPR regfile
464 initial_regs
= [0] * 32
465 initial_regs
[9] = 0x1234
466 initial_regs
[10] = 0x1111
467 initial_regs
[5] = 0x4321
468 initial_regs
[6] = 0x2223
470 # copy before running
471 expected_regs
= deepcopy(initial_regs
)
472 expected_regs
[1] = 0x5555
473 expected_regs
[2] = 0x3334
474 expected_regs
[3] = 2 # setvl places copy of VL here
476 with
Program(lst
, bigendian
=False) as program
:
477 sim
= self
.run_tst_program(program
, initial_regs
)
478 self
._check
_regs
(sim
, expected_regs
)
480 def test_svstep_add_1(self
):
481 """tests svstep with an add, when it reaches VL
482 lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
483 'sv.add 1.v, 5.v, 9.v',
484 "setvl. 0, 0, 1, 1, 0, 0",
485 'sv.add 1.v, 5.v, 9.v',
486 "setvl. 3, 0, 1, 1, 0, 0"
488 sequence is as follows:
489 * setvl sets VL=2 but also "Vertical First" mode.
490 this sets SVSTATE[SVF].
491 * first add, which has srcstep/dststep = 0, does add 1,5,9
492 * svstep EXPLICITLY walks srcstep/dststep to next element
493 * second add, which now has srcstep/dststep = 1, does add 2,6,10
494 * svstep EXPLICITLY walks srcstep/dststep to next element,
495 which now equals VL. srcstep and dststep are both set to
498 lst
= SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
499 'sv.add 1.v, 5.v, 9.v',
500 "setvl. 0, 0, 1, 1, 0, 0", # svstep
501 'sv.add 1.v, 5.v, 9.v',
502 "setvl. 3, 0, 1, 1, 0, 0", # svstep
503 "setvl 4, 0, 0, 0, 0, 0" # svstep
507 # SVSTATE (in this case, VL=2)
508 svstate
= SVP64State()
510 svstate
.maxvl
= 2 # MAXVL
511 print ("SVSTATE", bin(svstate
.asint()))
513 # initial values in GPR regfile
514 initial_regs
= [0] * 32
515 initial_regs
[9] = 0x1234
516 initial_regs
[10] = 0x1111
517 initial_regs
[5] = 0x4321
518 initial_regs
[6] = 0x2223
520 # copy before running
521 expected_regs
= deepcopy(initial_regs
)
522 expected_regs
[1] = 0x5555
523 expected_regs
[2] = 0x3334
524 expected_regs
[4] = 2 # setvl places copy of VL here
526 with
Program(lst
, bigendian
=False) as program
:
527 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
528 print ("SVSTATE after", bin(sim
.svstate
.asint()))
529 print (" vl", bin(sim
.svstate
.vl
))
530 print (" mvl", bin(sim
.svstate
.maxvl
))
531 print (" srcstep", bin(sim
.svstate
.srcstep
))
532 print (" dststep", bin(sim
.svstate
.dststep
))
533 print (" vfirst", bin(sim
.svstate
. vfirst
))
534 self
.assertEqual(sim
.svstate
.vl
, 2)
535 self
.assertEqual(sim
.svstate
.maxvl
, 2)
536 self
.assertEqual(sim
.svstate
.srcstep
, 0)
537 self
.assertEqual(sim
.svstate
.dststep
, 0)
538 # when end reached, vertical mode is exited
539 self
.assertEqual(sim
.svstate
.vfirst
, 0)
541 print(" CR0", bin(CR0
.get_range().value
))
542 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
543 self
.assertEqual(CR0
[CRFields
.LT
], 0)
544 self
.assertEqual(CR0
[CRFields
.GT
], 0)
545 self
.assertEqual(CR0
[CRFields
.SO
], 1)
547 # check registers as expected
548 self
._check
_regs
(sim
, expected_regs
)
550 def test_svstep_add_2(self
):
551 """tests svstep with a branch.
552 lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
553 'sv.add 1.v, 5.v, 9.v',
554 "setvl. 0, 0, 1, 1, 0, 0",
557 sequence is as follows:
558 * setvl sets VL=2 but also "Vertical First" mode.
560 * first time add, which has srcstep/dststep = 0, does add 1,5,9
561 * svstep EXPLICITLY walks srcstep/dststep to next element,
562 not yet met VL, so CR0.EQ is set to zero
563 * branch conditional checks bne on CR0, jumps back TWELVE bytes
564 because whilst branch is 32-bit the sv.add is 64-bit
565 * second time add, which now has srcstep/dststep = 1, does add 2,6,10
566 * svstep walks to next element, meets VL, so:
567 - srcstep and dststep set to zero
569 - MSR[SVF] is cleared
570 * branch conditional detects CR0.EQ=1 and FAILs the condition,
573 we therefore have an explicit "Vertical-First" system which can
574 have **MULTIPLE* instructions inside a loop, running each element 0
575 first, then looping back and running all element 1, then all element 2
578 lst
= SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
579 'sv.add 1.v, 5.v, 9.v',
580 "setvl. 0, 0, 1, 1, 0, 0", # svstep - this is 64-bit!
581 "bc 6, 3, -0xc" # branch to add (64-bit op so -0xc!)
585 # SVSTATE (in this case, VL=2)
586 svstate
= SVP64State()
588 svstate
.maxvl
= 2 # MAXVL
589 print ("SVSTATE", bin(svstate
.asint()))
591 # initial values in GPR regfile
592 initial_regs
= [0] * 32
593 initial_regs
[9] = 0x1234
594 initial_regs
[10] = 0x1111
595 initial_regs
[5] = 0x4321
596 initial_regs
[6] = 0x2223
598 # copy before running
599 expected_regs
= deepcopy(initial_regs
)
600 expected_regs
[1] = 0x5555
601 expected_regs
[2] = 0x3334
603 with
Program(lst
, bigendian
=False) as program
:
604 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
605 print ("SVSTATE after", bin(sim
.svstate
.asint()))
606 print (" vl", bin(sim
.svstate
.vl
))
607 print (" mvl", bin(sim
.svstate
.maxvl
))
608 print (" srcstep", bin(sim
.svstate
.srcstep
))
609 print (" dststep", bin(sim
.svstate
.dststep
))
610 print (" vfirst", bin(sim
.svstate
. vfirst
))
611 self
.assertEqual(sim
.svstate
.vl
, 2)
612 self
.assertEqual(sim
.svstate
.maxvl
, 2)
613 self
.assertEqual(sim
.svstate
.srcstep
, 0)
614 self
.assertEqual(sim
.svstate
.dststep
, 0)
615 # when end reached, vertical mode is exited
616 self
.assertEqual(sim
.svstate
.vfirst
, 0)
618 print(" CR0", bin(CR0
.get_range().value
))
619 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
620 self
.assertEqual(CR0
[CRFields
.LT
], 0)
621 self
.assertEqual(CR0
[CRFields
.GT
], 0)
622 self
.assertEqual(CR0
[CRFields
.SO
], 1)
624 # check registers as expected
625 self
._check
_regs
(sim
, expected_regs
)
627 def test_svremap(self
):
628 """svremap, see if values get set
630 lst
= SVP64Asm(["svremap 11, 0, 1, 2, 3, 3, 1",
634 with
Program(lst
, bigendian
=False) as program
:
635 sim
= self
.run_tst_program(program
)
636 svstate
= sim
.svstate
637 print ("SVREMAP after", bin(svstate
.value
))
638 print (" men", bin(svstate
.SVme
))
639 print (" mi0", bin(svstate
.mi0
))
640 print (" mi1", bin(svstate
.mi1
))
641 print (" mi2", bin(svstate
.mi2
))
642 print (" mo0", bin(svstate
.mo0
))
643 print (" mo1", bin(svstate
.mo1
))
644 print (" persist", bin(svstate
.RMpst
))
645 self
.assertEqual(svstate
.SVme
, 11)
646 self
.assertEqual(svstate
.mi0
, 0)
647 self
.assertEqual(svstate
.mi1
, 1)
648 self
.assertEqual(svstate
.mi2
, 2)
649 self
.assertEqual(svstate
.mo0
, 3)
650 self
.assertEqual(svstate
.mo1
, 3)
651 self
.assertEqual(svstate
.RMpst
, 1)
653 def test_svstep_iota(self
):
654 """tests svstep "straight", placing srcstep, dststep into vector
656 lst
= SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
657 "sv.svstep 0.v, 5, 1", # svstep get vector srcstep
658 "sv.svstep. 4.v, 6, 1", # svstep get vector dststep
663 svstate
= SVP64State()
665 #svstate.maxvl = 2 # MAXVL
666 print ("SVSTATE", bin(svstate
.asint()))
668 with
Program(lst
, bigendian
=False) as program
:
669 sim
= self
.run_tst_program(program
, svstate
=svstate
)
670 print ("SVSTATE after", bin(sim
.svstate
.asint()))
671 print (" vl", bin(sim
.svstate
.vl
))
672 print (" mvl", bin(sim
.svstate
.maxvl
))
673 print (" srcstep", bin(sim
.svstate
.srcstep
))
674 print (" dststep", bin(sim
.svstate
.dststep
))
675 print (" vfirst", bin(sim
.svstate
. vfirst
))
676 self
.assertEqual(sim
.svstate
.vl
, 4)
677 self
.assertEqual(sim
.svstate
.maxvl
, 4)
678 # svstep called four times, reset occurs, srcstep zero
679 self
.assertEqual(sim
.svstate
.srcstep
, 0)
680 self
.assertEqual(sim
.svstate
.dststep
, 0)
682 self
.assertEqual(sim
.gpr(0+i
), SelectableInt(i
, 64))
683 self
.assertEqual(sim
.gpr(4+i
), SelectableInt(i
, 64))
684 self
.assertEqual(sim
.svstate
.vfirst
, 0)
686 print(" CR0", bin(CR0
.get_range().value
))
687 self
.assertEqual(CR0
[CRFields
.EQ
], 0)
688 self
.assertEqual(CR0
[CRFields
.LT
], 0)
689 self
.assertEqual(CR0
[CRFields
.GT
], 0)
690 self
.assertEqual(CR0
[CRFields
.SO
], 1)
692 def test_svstep_iota_mask(self
):
693 """tests svstep "straight", placing srcstep, dststep into vector
695 lst
= SVP64Asm(["setvl 0, 0, 5, 0, 1, 1",
696 "sv.svstep/m=r30 0.v, 5, 1", # svstep get vector srcstep
697 "sv.svstep./m=r30 8.v, 6, 1", # svstep get vector dststep
702 svstate
= SVP64State()
704 #svstate.maxvl = 2 # MAXVL
705 print ("SVSTATE", bin(svstate
.asint()))
708 initial_regs
= [0] * 32
709 initial_regs
[30] = mask
711 with
Program(lst
, bigendian
=False) as program
:
712 sim
= self
.run_tst_program(program
, svstate
=svstate
,
713 initial_regs
=initial_regs
)
714 print ("SVSTATE after", bin(sim
.svstate
.asint()))
715 print (" vl", bin(sim
.svstate
.vl
))
716 print (" mvl", bin(sim
.svstate
.maxvl
))
717 print (" srcstep", bin(sim
.svstate
.srcstep
))
718 print (" dststep", bin(sim
.svstate
.dststep
))
719 print (" vfirst", bin(sim
.svstate
. vfirst
))
720 self
.assertEqual(sim
.svstate
.vl
, 5)
721 self
.assertEqual(sim
.svstate
.maxvl
, 5)
722 # svstep called four times, reset occurs, srcstep zero
723 self
.assertEqual(sim
.svstate
.srcstep
, 0)
724 self
.assertEqual(sim
.svstate
.dststep
, 0)
731 self
.assertEqual(sim
.gpr(0+i
), SelectableInt(tst
, 64))
732 self
.assertEqual(sim
.gpr(8+i
), SelectableInt(tst
, 64))
733 self
.assertEqual(sim
.svstate
.vfirst
, 0)
735 print(" CR4", bin(CR4
.get_range().value
))
736 self
.assertEqual(CR4
[CRFields
.EQ
], 0)
737 self
.assertEqual(CR4
[CRFields
.LT
], 0)
738 self
.assertEqual(CR4
[CRFields
.GT
], 0)
739 self
.assertEqual(CR4
[CRFields
.SO
], 0)
741 def run_tst_program(self
, prog
, initial_regs
=None,
744 if initial_regs
is None:
745 initial_regs
= [0] * 32
746 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
,
747 initial_sprs
=initial_sprs
)
752 if __name__
== "__main__":