src/openpower/decoder/isa/test_caller_setvl.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_svstep_1(self):
  25         lst = SVP64Asm(["setvl 0, 0, 9, 1, 1, 1",
  26                         "setvl 0, 0, 0, 1, 0, 0",
  27                         "setvl 0, 0, 0, 1, 0, 0"
  28                         ])
  29         lst = list(lst)
  30
  31         # SVSTATE (in this case, VL=4) which is going to get erased by setvl
  32         svstate = SVP64State()
  33         svstate.vl[0:7] = 4 # VL
  34         svstate.maxvl[0:7] = 4 # MAXVL
  35         print ("SVSTATE", bin(svstate.spr.asint()))
  36
  37         with Program(lst, bigendian=False) as program:
  38             sim = self.run_tst_program(program, svstate=svstate)
  39             print ("SVSTATE after", bin(sim.svstate.spr.asint()))
  40             print ("        vl", bin(sim.svstate.vl.asint(True)))
  41             print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
  42             print ("    srcstep", bin(sim.svstate.srcstep.asint(True)))
  43             print ("    dststep", bin(sim.svstate.dststep.asint(True)))
  44             self.assertEqual(sim.svstate.vl.asint(True), 10)
  45             self.assertEqual(sim.svstate.maxvl.asint(True), 10)
  46             self.assertEqual(sim.svstate.srcstep.asint(True), 2)
  47             self.assertEqual(sim.svstate.dststep.asint(True), 2)
  48             print("      gpr1", sim.gpr(0))
  49             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
  50             print("      msr", bin(sim.msr.value))
  51             self.assertEqual(sim.msr, SelectableInt(1<<(63-6), 64))
  52
  53     def test_svstep_2(self):
  54         """tests svstep when it reaches VL
  55         """
  56         lst = SVP64Asm(["setvl 0, 0, 1, 1, 1, 1",
  57                         "setvl. 0, 0, 0, 1, 0, 0",
  58                         "setvl. 0, 0, 0, 1, 0, 0"
  59                         ])
  60         lst = list(lst)
  61
  62         # SVSTATE (in this case, VL=2)
  63         svstate = SVP64State()
  64         svstate.vl[0:7] = 2 # VL
  65         svstate.maxvl[0:7] = 2 # MAXVL
  66         print ("SVSTATE", bin(svstate.spr.asint()))
  67
  68         with Program(lst, bigendian=False) as program:
  69             sim = self.run_tst_program(program, svstate=svstate)
  70             print ("SVSTATE after", bin(sim.svstate.spr.asint()))
  71             print ("        vl", bin(sim.svstate.vl.asint(True)))
  72             print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
  73             print ("    srcstep", bin(sim.svstate.srcstep.asint(True)))
  74             print ("    dststep", bin(sim.svstate.dststep.asint(True)))
  75             self.assertEqual(sim.svstate.vl.asint(True), 2)
  76             self.assertEqual(sim.svstate.maxvl.asint(True), 2)
  77             self.assertEqual(sim.svstate.srcstep.asint(True), 0)
  78             self.assertEqual(sim.svstate.dststep.asint(True), 0)
  79             print("      gpr1", sim.gpr(0))
  80             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
  81             # when end reached, vertical mode is exited
  82             print("      msr", bin(sim.msr.value))
  83             self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64))
  84             CR0 = sim.crl[0]
  85             print("      CR0", bin(CR0.get_range().value))
  86             self.assertEqual(CR0[CRFields.EQ], 1)
  87             self.assertEqual(CR0[CRFields.LT], 0)
  88             self.assertEqual(CR0[CRFields.GT], 0)
  89             self.assertEqual(CR0[CRFields.SO], 0)
  90
  91     def test_svstep_3(self):
  92         """tests svstep when it *doesn't* reach VL
  93         """
  94         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
  95                         "setvl. 0, 0, 0, 1, 0, 0",
  96                         "setvl. 0, 0, 0, 1, 0, 0"
  97                         ])
  98         lst = list(lst)
  99
 100         # SVSTATE (in this case, VL=2)
 101         svstate = SVP64State()
 102         svstate.vl[0:7] = 2 # VL
 103         svstate.maxvl[0:7] = 2 # MAXVL
 104         print ("SVSTATE", bin(svstate.spr.asint()))
 105
 106         with Program(lst, bigendian=False) as program:
 107             sim = self.run_tst_program(program, svstate=svstate)
 108             print ("SVSTATE after", bin(sim.svstate.spr.asint()))
 109             print ("        vl", bin(sim.svstate.vl.asint(True)))
 110             print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
 111             print ("    srcstep", bin(sim.svstate.srcstep.asint(True)))
 112             print ("    dststep", bin(sim.svstate.dststep.asint(True)))
 113             self.assertEqual(sim.svstate.vl.asint(True), 3)
 114             self.assertEqual(sim.svstate.maxvl.asint(True), 3)
 115             # svstep called twice, didn't reach VL, so srcstep/dststep both 2
 116             self.assertEqual(sim.svstate.srcstep.asint(True), 2)
 117             self.assertEqual(sim.svstate.dststep.asint(True), 2)
 118             print("      gpr1", sim.gpr(0))
 119             self.assertEqual(sim.gpr(0), SelectableInt(0, 64))
 120             print("      msr", bin(sim.msr.value))
 121             self.assertEqual(sim.msr, SelectableInt(1<<(63-6), 64))
 122             CR0 = sim.crl[0]
 123             print("      CR0", bin(CR0.get_range().value))
 124             self.assertEqual(CR0[CRFields.EQ], 0)
 125             self.assertEqual(CR0[CRFields.LT], 0)
 126             self.assertEqual(CR0[CRFields.GT], 1)
 127             self.assertEqual(CR0[CRFields.SO], 0)
 128
 129
 130     def test_setvl_1(self):
 131         lst = SVP64Asm(["setvl 1, 0, 9, 0, 1, 1",
 132                         ])
 133         lst = list(lst)
 134
 135         # SVSTATE (in this case, VL=2)
 136         svstate = SVP64State()
 137         svstate.vl[0:7] = 2 # VL
 138         svstate.maxvl[0:7] = 2 # MAXVL
 139         print ("SVSTATE", bin(svstate.spr.asint()))
 140
 141         with Program(lst, bigendian=False) as program:
 142             sim = self.run_tst_program(program, svstate=svstate)
 143             print ("SVSTATE after", bin(sim.svstate.spr.asint()))
 144             print ("        vl", bin(sim.svstate.vl.asint(True)))
 145             print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
 146             self.assertEqual(sim.svstate.vl.asint(True), 10)
 147             self.assertEqual(sim.svstate.maxvl.asint(True), 10)
 148             self.assertEqual(sim.svstate.maxvl.asint(True), 10)
 149             print("      gpr1", sim.gpr(1))
 150             self.assertEqual(sim.gpr(1), SelectableInt(10, 64))
 151
 152
 153     def test_sv_add(self):
 154         # sets VL=2 then adds:
 155         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 156         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 157         isa = SVP64Asm(["setvl 3, 0, 1, 0, 1, 1",
 158                         'sv.add 1.v, 5.v, 9.v'
 159                        ])
 160         lst = list(isa)
 161         print ("listing", lst)
 162
 163         # initial values in GPR regfile
 164         initial_regs = [0] * 32
 165         initial_regs[9] = 0x1234
 166         initial_regs[10] = 0x1111
 167         initial_regs[5] = 0x4321
 168         initial_regs[6] = 0x2223
 169
 170         # copy before running
 171         expected_regs = deepcopy(initial_regs)
 172         expected_regs[1] = 0x5555
 173         expected_regs[2] = 0x3334
 174         expected_regs[3] = 2       # setvl places copy of VL here
 175
 176         with Program(lst, bigendian=False) as program:
 177             sim = self.run_tst_program(program, initial_regs)
 178             self._check_regs(sim, expected_regs)
 179
 180     def run_tst_program(self, prog, initial_regs=None,
 181                               svstate=None):
 182         if initial_regs is None:
 183             initial_regs = [0] * 32
 184         simulator = run_tst(prog, initial_regs, svstate=svstate)
 185         simulator.gpr.dump()
 186         return simulator
 187
 188
 189 if __name__ == "__main__":
 190     unittest.main()
 191