1 from nmutil
.formaltest
import FHDLTestCase
3 from openpower
.simulator
.program
import Program
4 from openpower
.decoder
.selectable_int
import SelectableInt
5 from openpower
.decoder
.isa
.test_runner
import run_tst
8 class DecoderTestCase(FHDLTestCase
):
10 def test_0_proof_regression_rlwnm(self
):
11 lst
= ["rlwnm 3, 1, 2, 16, 20"]
12 initial_regs
= [0] * 32
13 #initial_regs[1] =0x7ffdbffb91b906b9
14 initial_regs
[1] = 0x11faafff1111aa11
17 with
Program(lst
, bigendian
=False) as program
:
18 sim
= self
.run_tst_program(program
, initial_regs
)
20 def test_case_srw_1(self
):
21 lst
= ["sraw 3, 1, 2"]
22 initial_regs
= [0] * 32
23 initial_regs
[1] = 0x12345678
25 with
Program(lst
, bigendian
=False) as program
:
26 sim
= self
.run_tst_program(program
, initial_regs
)
27 self
.assertEqual(sim
.gpr(3), SelectableInt(0x123456, 64))
29 def test_case_srw_2(self
):
30 lst
= ["sraw 3, 1, 2"]
31 initial_regs
= [0] * 32
32 initial_regs
[1] = 0x82345678 # test the carry
34 with
Program(lst
, bigendian
=False) as program
:
35 sim
= self
.run_tst_program(program
, initial_regs
)
36 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffffffffff823456, 64))
38 def test_case_sld_rb_too_big(self
):
41 initial_regs
= [0] * 32
42 initial_regs
[1] = 0xffffffffffffffff
43 initial_regs
[4] = 64 # too big, output should be zero
44 with
Program(lst
, bigendian
=False) as program
:
45 sim
= self
.run_tst_program(program
, initial_regs
)
46 self
.assertEqual(sim
.gpr(3), SelectableInt(0, 64))
48 def test_case_sld_rb_is_zero(self
):
50 initial_regs
= [0] * 32
51 initial_regs
[1] = 0x8000000000000000
52 initial_regs
[4] = 0 # no shift; output should equal input
53 with
Program(lst
, bigendian
=False) as program
:
54 sim
= self
.run_tst_program(program
, initial_regs
)
55 self
.assertEqual(sim
.gpr(3), SelectableInt(initial_regs
[1], 64))
57 def test_case_shift_once(self
):
60 initial_regs
= [0] * 32
61 initial_regs
[1] = 0x80000000
62 initial_regs
[2] = 0x40
63 initial_regs
[4] = 0x00
64 with
Program(lst
, bigendian
=False) as program
:
65 sim
= self
.run_tst_program(program
, initial_regs
)
66 self
.assertEqual(sim
.gpr(1), SelectableInt(initial_regs
[1], 64))
68 def test_case_rlwinm_1(self
):
69 lst
= ["rlwinm 3, 1, 1, 31, 31"] # Extracts sign bit
70 initial_regs
= [0] * 32
71 initial_regs
[1] = 0x8fffffff
72 with
Program(lst
, bigendian
=False) as program
:
73 sim
= self
.run_tst_program(program
, initial_regs
)
74 self
.assertEqual(sim
.gpr(3), SelectableInt(1, 64))
76 def test_case_rlwinm_2(self
):
77 lst
= ["rlwinm 3, 1, 1, 0, 30"]
78 initial_regs
= [0] * 32
79 initial_regs
[1] = 0xf1110001
80 with
Program(lst
, bigendian
=False) as program
:
81 sim
= self
.run_tst_program(program
, initial_regs
)
82 self
.assertEqual(sim
.gpr(3), SelectableInt(0xe2220002, 64))
84 def test_case_rlwinm_3(self
):
85 lst
= ["rlwinm 3, 1, 0, 16, 31"] # Clear high-order 16 bits
86 initial_regs
= [0] * 32
87 initial_regs
[1] = 0xebeb1888
88 with
Program(lst
, bigendian
=False) as program
:
89 sim
= self
.run_tst_program(program
, initial_regs
)
90 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1888, 64))
92 def test_case_rlwimi_1(self
):
93 lst
= ["rlwimi 3, 1, 31, 0, 0"]
94 initial_regs
= [0] * 32
96 initial_regs
[3] = 0x7fffffff
97 with
Program(lst
, bigendian
=False) as program
:
98 sim
= self
.run_tst_program(program
, initial_regs
)
99 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffffffff, 64))
101 def test_case_rlwimi_2(self
):
102 lst
= ["rlwimi 3, 1, 16, 8, 15"]
103 initial_regs
= [0] * 32
104 initial_regs
[1] = 0xcc
105 initial_regs
[3] = 0x7f00ffff
106 with
Program(lst
, bigendian
=False) as program
:
107 sim
= self
.run_tst_program(program
, initial_regs
)
108 self
.assertEqual(sim
.gpr(3), SelectableInt(0x7fccffff, 64))
110 def test_case_rlwnm_1(self
):
111 lst
= ["rlwnm 3, 1, 2, 0, 31"]
112 initial_regs
= [0] * 32
113 initial_regs
[1] = 0x111
115 with
Program(lst
, bigendian
=False) as program
:
116 sim
= self
.run_tst_program(program
, initial_regs
)
117 self
.assertEqual(sim
.gpr(3), SelectableInt(0x222, 64))
119 def test_case_rlwnm_2(self
):
120 lst
= ["rlwnm 3, 1, 2, 8, 11"]
121 initial_regs
= [0] * 32
122 initial_regs
[1] = 0xfebaacda
124 with
Program(lst
, bigendian
=False) as program
:
125 sim
= self
.run_tst_program(program
, initial_regs
)
126 self
.assertEqual(sim
.gpr(3), SelectableInt(0xd00000, 64))
128 def test_case_rldic_1(self
):
129 lst
= ["rldic 3, 1, 8, 31"] # Simple rotate and clear
130 initial_regs
= [0] * 32
131 initial_regs
[1] = 0x0100ffff00000111
132 with
Program(lst
, bigendian
=False) as program
:
133 sim
= self
.run_tst_program(program
, initial_regs
)
134 self
.assertEqual(sim
.gpr(3), SelectableInt(0x11100, 64))
136 def test_case_rldic_2(self
):
137 lst
= ["rldic 3, 1, 0, 51"] # No rotate and clear
138 initial_regs
= [0] * 32
139 initial_regs
[1] = 0x0100ffff00000fff
140 with
Program(lst
, bigendian
=False) as program
:
141 sim
= self
.run_tst_program(program
, initial_regs
)
142 self
.assertEqual(sim
.gpr(3), SelectableInt(0xfff, 64))
144 def test_case_rldicl_1(self
):
145 lst
= ["rldicl 3, 1, 8, 44"] # Simple rotate with left clear
146 initial_regs
= [0] * 32
147 initial_regs
[1] = 0x0100ffff00000111
148 with
Program(lst
, bigendian
=False) as program
:
149 sim
= self
.run_tst_program(program
, initial_regs
)
150 self
.assertEqual(sim
.gpr(3), SelectableInt(0x11101, 64))
152 def test_case_rldicl_2(self
):
153 lst
= ["rldicl 3, 1, 32, 47"] # Rotate right and clear
154 initial_regs
= [0] * 32
155 initial_regs
[1] = 0x1000dead0000111c
156 with
Program(lst
, bigendian
=False) as program
:
157 sim
= self
.run_tst_program(program
, initial_regs
)
158 self
.assertEqual(sim
.gpr(3), SelectableInt(0xdead, 64))
160 def test_case_rldicr_1(self
):
161 lst
= ["rldicr 3, 1, 16, 15"] # Simple rotate with right clear
162 initial_regs
= [0] * 32
163 initial_regs
[1] = 0x0100ffffe0000111
164 with
Program(lst
, bigendian
=False) as program
:
165 sim
= self
.run_tst_program(program
, initial_regs
)
166 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffff000000000000, 64))
168 def test_case_rldicr_2(self
):
169 lst
= ["rldicr 3, 1, 32, 32"] # Rotate right and clear
170 initial_regs
= [0] * 32
171 initial_regs
[1] = 0x1000caef0000dead
172 with
Program(lst
, bigendian
=False) as program
:
173 sim
= self
.run_tst_program(program
, initial_regs
)
174 self
.assertEqual(sim
.gpr(3), SelectableInt(0xdead00000000, 64))
176 def test_case_regression_extswsli_1(self
):
177 lst
= [f
"extswsli 3, 1, 31"]
178 initial_regs
= [0] * 32
179 initial_regs
[1] = 0x5678
180 with
Program(lst
, bigendian
=False) as program
:
181 sim
= self
.run_tst_program(program
, initial_regs
)
182 self
.assertEqual(sim
.gpr(3), SelectableInt(0x2b3c00000000, 64))
184 def test_case_regression_extswsli_2(self
):
185 lst
= [f
"extswsli 3, 1, 7"]
186 initial_regs
= [0] * 32
187 initial_regs
[1] = 0x3ffffd7377f19fdd
188 with
Program(lst
, bigendian
=False) as program
:
189 sim
= self
.run_tst_program(program
, initial_regs
)
190 self
.assertEqual(sim
.gpr(3), SelectableInt(0x3bf8cfee80, 64))
192 def test_case_regression_extswsli_3(self
):
193 lst
= [f
"extswsli 3, 1, 0"]
194 initial_regs
= [0] * 32
195 initial_regs
[1] = 0x0000010180122900
196 with
Program(lst
, bigendian
=False) as program
:
197 sim
= self
.run_tst_program(program
, initial_regs
)
198 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffffffff80122900, 64))
200 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_mem
=None):
201 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
)
206 if __name__
== "__main__":