1 from nmutil
.formaltest
import FHDLTestCase
3 from openpower
.simulator
.program
import Program
4 from openpower
.decoder
.selectable_int
import SelectableInt
5 from openpower
.decoder
.isa
.test_runner
import run_tst
8 class DecoderTestCase(FHDLTestCase
):
10 def test_0_proof_regression_rlwnm(self
):
11 lst
= ["rlwnm 3, 1, 2, 16, 20"]
12 initial_regs
= [0] * 32
13 #initial_regs[1] =0x7ffdbffb91b906b9
14 initial_regs
[1] = 0x11faafff1111aa11
17 with
Program(lst
, bigendian
=False) as program
:
18 sim
= self
.run_tst_program(program
, initial_regs
)
19 self
.assertEqual(sim
.gpr(3), SelectableInt(0x8800, 64))
21 def test_case_srw_1(self
):
22 lst
= ["sraw 3, 1, 2"]
23 initial_regs
= [0] * 32
24 initial_regs
[1] = 0x12345678
26 with
Program(lst
, bigendian
=False) as program
:
27 sim
= self
.run_tst_program(program
, initial_regs
)
28 self
.assertEqual(sim
.gpr(3), SelectableInt(0x123456, 64))
30 def test_case_srw_2(self
):
31 lst
= ["sraw 3, 1, 2"]
32 initial_regs
= [0] * 32
33 initial_regs
[1] = 0x82345678 # test the carry
35 with
Program(lst
, bigendian
=False) as program
:
36 sim
= self
.run_tst_program(program
, initial_regs
)
37 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffffffffff823456, 64))
39 def test_case_sld_rb_too_big(self
):
42 initial_regs
= [0] * 32
43 initial_regs
[1] = 0xffffffffffffffff
44 initial_regs
[4] = 64 # too big, output should be zero
45 with
Program(lst
, bigendian
=False) as program
:
46 sim
= self
.run_tst_program(program
, initial_regs
)
47 self
.assertEqual(sim
.gpr(3), SelectableInt(0, 64))
49 def test_case_sld_rb_is_zero(self
):
51 initial_regs
= [0] * 32
52 initial_regs
[1] = 0x8000000000000000
53 initial_regs
[4] = 0 # no shift; output should equal input
54 with
Program(lst
, bigendian
=False) as program
:
55 sim
= self
.run_tst_program(program
, initial_regs
)
56 self
.assertEqual(sim
.gpr(3), SelectableInt(initial_regs
[1], 64))
58 def test_case_shift_once(self
):
61 initial_regs
= [0] * 32
62 initial_regs
[1] = 0x80000000
63 initial_regs
[2] = 0x40
64 initial_regs
[4] = 0x00
65 with
Program(lst
, bigendian
=False) as program
:
66 sim
= self
.run_tst_program(program
, initial_regs
)
67 self
.assertEqual(sim
.gpr(1), SelectableInt(initial_regs
[1], 64))
69 def test_case_rlwinm_1(self
):
70 lst
= ["rlwinm 3, 1, 1, 31, 31"] # Extracts sign bit
71 initial_regs
= [0] * 32
72 initial_regs
[1] = 0x8fffffff
73 with
Program(lst
, bigendian
=False) as program
:
74 sim
= self
.run_tst_program(program
, initial_regs
)
75 self
.assertEqual(sim
.gpr(3), SelectableInt(1, 64))
77 def test_case_rlwinm_2(self
):
78 lst
= ["rlwinm 3, 1, 1, 0, 30"]
79 initial_regs
= [0] * 32
80 initial_regs
[1] = 0xf1110001
81 with
Program(lst
, bigendian
=False) as program
:
82 sim
= self
.run_tst_program(program
, initial_regs
)
83 self
.assertEqual(sim
.gpr(3), SelectableInt(0xe2220002, 64))
85 def test_case_rlwinm_3(self
):
86 lst
= ["rlwinm 3, 1, 0, 16, 31"] # Clear high-order 16 bits
87 initial_regs
= [0] * 32
88 initial_regs
[1] = 0xebeb1888
89 with
Program(lst
, bigendian
=False) as program
:
90 sim
= self
.run_tst_program(program
, initial_regs
)
91 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1888, 64))
93 def test_case_rlwimi_1(self
):
94 lst
= ["rlwimi 3, 1, 31, 0, 0"]
95 initial_regs
= [0] * 32
97 initial_regs
[3] = 0x7fffffff
98 with
Program(lst
, bigendian
=False) as program
:
99 sim
= self
.run_tst_program(program
, initial_regs
)
100 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffffffff, 64))
102 def test_case_rlwimi_2(self
):
103 lst
= ["rlwimi 3, 1, 16, 8, 15"]
104 initial_regs
= [0] * 32
105 initial_regs
[1] = 0xcc
106 initial_regs
[3] = 0x7f00ffff
107 with
Program(lst
, bigendian
=False) as program
:
108 sim
= self
.run_tst_program(program
, initial_regs
)
109 self
.assertEqual(sim
.gpr(3), SelectableInt(0x7fccffff, 64))
111 def test_case_rlwnm_1(self
):
112 lst
= ["rlwnm 3, 1, 2, 0, 31"]
113 initial_regs
= [0] * 32
114 initial_regs
[1] = 0x111
116 with
Program(lst
, bigendian
=False) as program
:
117 sim
= self
.run_tst_program(program
, initial_regs
)
118 self
.assertEqual(sim
.gpr(3), SelectableInt(0x222, 64))
120 def test_case_rlwnm_2(self
):
121 lst
= ["rlwnm 3, 1, 2, 8, 11"]
122 initial_regs
= [0] * 32
123 initial_regs
[1] = 0xfebaacda
125 with
Program(lst
, bigendian
=False) as program
:
126 sim
= self
.run_tst_program(program
, initial_regs
)
127 self
.assertEqual(sim
.gpr(3), SelectableInt(0xd00000, 64))
129 def test_case_rldic_1(self
):
130 lst
= ["rldic 3, 1, 8, 31"] # Simple rotate and clear
131 initial_regs
= [0] * 32
132 initial_regs
[1] = 0x0100ffff00000111
133 with
Program(lst
, bigendian
=False) as program
:
134 sim
= self
.run_tst_program(program
, initial_regs
)
135 self
.assertEqual(sim
.gpr(3), SelectableInt(0x11100, 64))
137 def test_case_rldic_2(self
):
138 lst
= ["rldic 3, 1, 0, 51"] # No rotate and clear
139 initial_regs
= [0] * 32
140 initial_regs
[1] = 0x0100ffff00000fff
141 with
Program(lst
, bigendian
=False) as program
:
142 sim
= self
.run_tst_program(program
, initial_regs
)
143 self
.assertEqual(sim
.gpr(3), SelectableInt(0xfff, 64))
145 def test_case_rldicl_1(self
):
146 lst
= ["rldicl 3, 1, 8, 44"] # Simple rotate with left clear
147 initial_regs
= [0] * 32
148 initial_regs
[1] = 0x0100ffff00000111
149 with
Program(lst
, bigendian
=False) as program
:
150 sim
= self
.run_tst_program(program
, initial_regs
)
151 self
.assertEqual(sim
.gpr(3), SelectableInt(0x11101, 64))
153 def test_case_rldicl_2(self
):
154 lst
= ["rldicl 3, 1, 32, 47"] # Rotate right and clear
155 initial_regs
= [0] * 32
156 initial_regs
[1] = 0x1000dead0000111c
157 with
Program(lst
, bigendian
=False) as program
:
158 sim
= self
.run_tst_program(program
, initial_regs
)
159 self
.assertEqual(sim
.gpr(3), SelectableInt(0xdead, 64))
161 def test_case_rldicr_1(self
):
162 lst
= ["rldicr 3, 1, 16, 15"] # Simple rotate with right clear
163 initial_regs
= [0] * 32
164 initial_regs
[1] = 0x0100ffffe0000111
165 with
Program(lst
, bigendian
=False) as program
:
166 sim
= self
.run_tst_program(program
, initial_regs
)
167 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffff000000000000, 64))
169 def test_case_rldicr_2(self
):
170 lst
= ["rldicr 3, 1, 32, 32"] # Rotate right and clear
171 initial_regs
= [0] * 32
172 initial_regs
[1] = 0x1000caef0000dead
173 with
Program(lst
, bigendian
=False) as program
:
174 sim
= self
.run_tst_program(program
, initial_regs
)
175 self
.assertEqual(sim
.gpr(3), SelectableInt(0xdead00000000, 64))
177 def test_case_regression_extswsli_1(self
):
178 lst
= [f
"extswsli 3, 1, 31"]
179 initial_regs
= [0] * 32
180 initial_regs
[1] = 0x5678
181 with
Program(lst
, bigendian
=False) as program
:
182 sim
= self
.run_tst_program(program
, initial_regs
)
183 self
.assertEqual(sim
.gpr(3), SelectableInt(0x2b3c00000000, 64))
185 def test_case_regression_extswsli_2(self
):
186 lst
= [f
"extswsli 3, 1, 7"]
187 initial_regs
= [0] * 32
188 initial_regs
[1] = 0x3ffffd7377f19fdd
189 with
Program(lst
, bigendian
=False) as program
:
190 sim
= self
.run_tst_program(program
, initial_regs
)
191 self
.assertEqual(sim
.gpr(3), SelectableInt(0x3bf8cfee80, 64))
193 def test_case_regression_extswsli_3(self
):
194 lst
= [f
"extswsli 3, 1, 0"]
195 initial_regs
= [0] * 32
196 initial_regs
[1] = 0x0000010180122900
197 with
Program(lst
, bigendian
=False) as program
:
198 sim
= self
.run_tst_program(program
, initial_regs
)
199 self
.assertEqual(sim
.gpr(3), SelectableInt(0xffffffff80122900, 64))
201 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_mem
=None):
202 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
)
207 if __name__
== "__main__":