src/openpower/decoder/isa/test_caller_shift_rot.py

   1 from nmutil.formaltest import FHDLTestCase
   2 import unittest
   3 from openpower.test.state import ExpectedState
   4 from openpower.simulator.program import Program
   5 from openpower.decoder.selectable_int import SelectableInt
   6 from openpower.decoder.isa.test_runner import run_tst
   7
   8
   9 class DecoderTestCase(FHDLTestCase):
  10
  11     def test_0_proof_regression_rlwnm(self):
  12         lst = ["rlwnm 3, 1, 2, 16, 20"]
  13         initial_regs = [0] * 32
  14         #initial_regs[1] =0x7ffdbffb91b906b9
  15         initial_regs[1] = 0x11faafff1111aa11
  16         #initial_regs[2] = 31
  17         initial_regs[2] = 11
  18         # Trying to get a blank expected state, no bueno on test running
  19         # it doesn't care what goes there
  20         e = yield from ExpectedState()
  21         with Program(lst, bigendian=False) as program:
  22             sim = self.run_tst_program(program, initial_regs)
  23             self.assertEqual(sim.gpr(3), SelectableInt(0x8800, 64))
  24
  25     """
  26     def test_case_srw_1(self):
  27         lst = ["sraw 3, 1, 2"]
  28         initial_regs = [0] * 32
  29         initial_regs[1] = 0x12345678
  30         initial_regs[2] = 8
  31         with Program(lst, bigendian=False) as program:
  32             sim = self.run_tst_program(program, initial_regs)
  33             self.assertEqual(sim.gpr(3), SelectableInt(0x123456, 64))
  34
  35     def test_case_srw_2(self):
  36         lst = ["sraw 3, 1, 2"]
  37         initial_regs = [0] * 32
  38         initial_regs[1] = 0x82345678  # test the carry
  39         initial_regs[2] = 8
  40         with Program(lst, bigendian=False) as program:
  41             sim = self.run_tst_program(program, initial_regs)
  42             self.assertEqual(sim.gpr(3), SelectableInt(0xffffffffff823456, 64))
  43
  44     def test_case_sld_rb_too_big(self):
  45         lst = ["sld 3, 1, 4",
  46                ]
  47         initial_regs = [0] * 32
  48         initial_regs[1] = 0xffffffffffffffff
  49         initial_regs[4] = 64  # too big, output should be zero
  50         with Program(lst, bigendian=False) as program:
  51             sim = self.run_tst_program(program, initial_regs)
  52             self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
  53
  54     def test_case_sld_rb_is_zero(self):
  55         lst = ["sld 3, 1, 4"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 0x8000000000000000
  58         initial_regs[4] = 0  # no shift; output should equal input
  59         with Program(lst, bigendian=False) as program:
  60             sim = self.run_tst_program(program, initial_regs)
  61             self.assertEqual(sim.gpr(3), SelectableInt(initial_regs[1], 64))
  62
  63     def test_case_shift_once(self):
  64         lst = ["slw 3, 1, 4",
  65                "slw 3, 1, 2"]
  66         initial_regs = [0] * 32
  67         initial_regs[1] = 0x80000000
  68         initial_regs[2] = 0x40
  69         initial_regs[4] = 0x00
  70         with Program(lst, bigendian=False) as program:
  71             sim = self.run_tst_program(program, initial_regs)
  72             self.assertEqual(sim.gpr(1), SelectableInt(initial_regs[1], 64))
  73
  74     def test_case_rlwinm_1(self):
  75         lst = ["rlwinm 3, 1, 1, 31, 31"]  # Extracts sign bit
  76         initial_regs = [0] * 32
  77         initial_regs[1] = 0x8fffffff
  78         with Program(lst, bigendian=False) as program:
  79             sim = self.run_tst_program(program, initial_regs)
  80             self.assertEqual(sim.gpr(3), SelectableInt(1, 64))
  81
  82     def test_case_rlwinm_2(self):
  83         lst = ["rlwinm 3, 1, 1, 0, 30"]
  84         initial_regs = [0] * 32
  85         initial_regs[1] = 0xf1110001
  86         with Program(lst, bigendian=False) as program:
  87             sim = self.run_tst_program(program, initial_regs)
  88             self.assertEqual(sim.gpr(3), SelectableInt(0xe2220002, 64))
  89
  90     def test_case_rlwinm_3(self):
  91         lst = ["rlwinm 3, 1, 0, 16, 31"]  # Clear high-order 16 bits
  92         initial_regs = [0] * 32
  93         initial_regs[1] = 0xebeb1888
  94         with Program(lst, bigendian=False) as program:
  95             sim = self.run_tst_program(program, initial_regs)
  96             self.assertEqual(sim.gpr(3), SelectableInt(0x1888, 64))
  97
  98     def test_case_rlwimi_1(self):
  99         lst = ["rlwimi 3, 1, 31, 0, 0"]
 100         initial_regs = [0] * 32
 101         initial_regs[1] = 0x1
 102         initial_regs[3] = 0x7fffffff
 103         with Program(lst, bigendian=False) as program:
 104             sim = self.run_tst_program(program, initial_regs)
 105             self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff, 64))
 106
 107     def test_case_rlwimi_2(self):
 108         lst = ["rlwimi 3, 1, 16, 8, 15"]
 109         initial_regs = [0] * 32
 110         initial_regs[1] = 0xcc
 111         initial_regs[3] = 0x7f00ffff
 112         with Program(lst, bigendian=False) as program:
 113             sim = self.run_tst_program(program, initial_regs)
 114             self.assertEqual(sim.gpr(3), SelectableInt(0x7fccffff, 64))
 115
 116     def test_case_rlwnm_1(self):
 117         lst = ["rlwnm 3, 1, 2, 0, 31"]
 118         initial_regs = [0] * 32
 119         initial_regs[1] = 0x111
 120         initial_regs[2] = 1
 121         with Program(lst, bigendian=False) as program:
 122             sim = self.run_tst_program(program, initial_regs)
 123             self.assertEqual(sim.gpr(3), SelectableInt(0x222, 64))
 124
 125     def test_case_rlwnm_2(self):
 126         lst = ["rlwnm 3, 1, 2, 8, 11"]
 127         initial_regs = [0] * 32
 128         initial_regs[1] = 0xfebaacda
 129         initial_regs[2] = 16
 130         with Program(lst, bigendian=False) as program:
 131             sim = self.run_tst_program(program, initial_regs)
 132             self.assertEqual(sim.gpr(3), SelectableInt(0xd00000, 64))
 133
 134     def test_case_rldic_1(self):
 135         lst = ["rldic 3, 1, 8, 31"]  # Simple rotate and clear
 136         initial_regs = [0] * 32
 137         initial_regs[1] = 0x0100ffff00000111
 138         with Program(lst, bigendian=False) as program:
 139             sim = self.run_tst_program(program, initial_regs)
 140             self.assertEqual(sim.gpr(3), SelectableInt(0x11100, 64))
 141
 142     def test_case_rldic_2(self):
 143         lst = ["rldic 3, 1, 0, 51"]  # No rotate and clear
 144         initial_regs = [0] * 32
 145         initial_regs[1] = 0x0100ffff00000fff
 146         with Program(lst, bigendian=False) as program:
 147             sim = self.run_tst_program(program, initial_regs)
 148             self.assertEqual(sim.gpr(3), SelectableInt(0xfff, 64))
 149
 150     def test_case_rldicl_1(self):
 151         lst = ["rldicl 3, 1, 8, 44"]  # Simple rotate with left clear
 152         initial_regs = [0] * 32
 153         initial_regs[1] = 0x0100ffff00000111
 154         with Program(lst, bigendian=False) as program:
 155             sim = self.run_tst_program(program, initial_regs)
 156             self.assertEqual(sim.gpr(3), SelectableInt(0x11101, 64))
 157
 158     def test_case_rldicl_2(self):
 159         lst = ["rldicl 3, 1, 32, 47"]  # Rotate right and clear
 160         initial_regs = [0] * 32
 161         initial_regs[1] = 0x1000dead0000111c
 162         with Program(lst, bigendian=False) as program:
 163             sim = self.run_tst_program(program, initial_regs)
 164             self.assertEqual(sim.gpr(3), SelectableInt(0xdead, 64))
 165
 166     def test_case_rldicr_1(self):
 167         lst = ["rldicr 3, 1, 16, 15"]  # Simple rotate with right clear
 168         initial_regs = [0] * 32
 169         initial_regs[1] = 0x0100ffffe0000111
 170         with Program(lst, bigendian=False) as program:
 171             sim = self.run_tst_program(program, initial_regs)
 172             self.assertEqual(sim.gpr(3), SelectableInt(0xffff000000000000, 64))
 173
 174     def test_case_rldicr_2(self):
 175         lst = ["rldicr 3, 1, 32, 32"]  # Rotate right and clear
 176         initial_regs = [0] * 32
 177         initial_regs[1] = 0x1000caef0000dead
 178         with Program(lst, bigendian=False) as program:
 179             sim = self.run_tst_program(program, initial_regs)
 180             self.assertEqual(sim.gpr(3), SelectableInt(0xdead00000000, 64))
 181
 182     def test_case_regression_extswsli_1(self):
 183         lst = [f"extswsli 3, 1, 31"]
 184         initial_regs = [0] * 32
 185         initial_regs[1] = 0x5678
 186         with Program(lst, bigendian=False) as program:
 187             sim = self.run_tst_program(program, initial_regs)
 188             self.assertEqual(sim.gpr(3), SelectableInt(0x2b3c00000000, 64))
 189
 190     def test_case_regression_extswsli_2(self):
 191         lst = [f"extswsli 3, 1, 7"]
 192         initial_regs = [0] * 32
 193         initial_regs[1] = 0x3ffffd7377f19fdd
 194         with Program(lst, bigendian=False) as program:
 195             sim = self.run_tst_program(program, initial_regs)
 196             self.assertEqual(sim.gpr(3), SelectableInt(0x3bf8cfee80, 64))
 197
 198     def test_case_regression_extswsli_3(self):
 199         lst = [f"extswsli 3, 1, 0"]
 200         initial_regs = [0] * 32
 201         initial_regs[1] = 0x0000010180122900
 202         with Program(lst, bigendian=False) as program:
 203             sim = self.run_tst_program(program, initial_regs)
 204             self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff80122900, 64))
 205     """
 206
 207     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None):
 208         simulator = run_tst(prog, initial_regs, mem=initial_mem)
 209         simulator.gpr.dump()
 210         return simulator
 211
 212 if __name__ == "__main__":
 213     unittest.main()