1 from nmutil
.formaltest
import FHDLTestCase
3 from openpower
.decoder
.power_enums
import XER_bits
4 from openpower
.test
.state
import ExpectedState
5 from openpower
.simulator
.program
import Program
6 from openpower
.decoder
.selectable_int
import SelectableInt
7 from openpower
.decoder
.isa
.test_runner
import run_tst
10 class DecoderTestCase(FHDLTestCase
):
12 def test_0_proof_regression_rlwnm(self
):
13 lst
= ["rlwnm 3, 1, 2, 16, 20"]
14 initial_regs
= [0] * 32
15 #initial_regs[1] =0x7ffdbffb91b906b9
16 initial_regs
[1] = 0x11faafff1111aa11
19 # set expected (intregs, pc, [crregs], so, ov, ca)
20 e
= ExpectedState(initial_regs
, 4, [0,0,0,0,0,0,0,0], 0, 0, 0)
22 with
Program(lst
, bigendian
=False) as program
:
23 sim
= self
.run_tst_program(program
, initial_regs
)
24 self
.check_regs(sim
, e
)
26 def test_case_srw_1(self
):
27 lst
= ["sraw 3, 1, 2"]
28 initial_regs
= [0] * 32
29 initial_regs
[1] = 0x12345678
31 e
= ExpectedState(initial_regs
, 4, [0,0,0,0,0,0,0,0], 0, 0, 0)
32 e
.intregs
[3] = 0x123456
33 with
Program(lst
, bigendian
=False) as program
:
34 sim
= self
.run_tst_program(program
, initial_regs
)
35 self
.check_regs(sim
, e
)
37 def test_case_srw_2(self):
38 lst = ["sraw 3, 1, 2"]
39 initial_regs = [0] * 32
40 initial_regs[1] = 0x82345678 # test the carry
42 with Program(lst, bigendian=False) as program:
43 sim = self.run_tst_program(program, initial_regs)
44 self.assertEqual(sim.gpr(3), SelectableInt(0xffffffffff823456, 64))
46 def test_case_sld_rb_too_big(self):
49 initial_regs = [0] * 32
50 initial_regs[1] = 0xffffffffffffffff
51 initial_regs[4] = 64 # too big, output should be zero
52 with Program(lst, bigendian=False) as program:
53 sim = self.run_tst_program(program, initial_regs)
54 self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
56 def test_case_sld_rb_is_zero(self):
58 initial_regs = [0] * 32
59 initial_regs[1] = 0x8000000000000000
60 initial_regs[4] = 0 # no shift; output should equal input
61 with Program(lst, bigendian=False) as program:
62 sim = self.run_tst_program(program, initial_regs)
63 self.assertEqual(sim.gpr(3), SelectableInt(initial_regs[1], 64))
65 def test_case_shift_once(self):
68 initial_regs = [0] * 32
69 initial_regs[1] = 0x80000000
70 initial_regs[2] = 0x40
71 initial_regs[4] = 0x00
72 with Program(lst, bigendian=False) as program:
73 sim = self.run_tst_program(program, initial_regs)
74 self.assertEqual(sim.gpr(1), SelectableInt(initial_regs[1], 64))
76 def test_case_rlwinm_1(self):
77 lst = ["rlwinm 3, 1, 1, 31, 31"] # Extracts sign bit
78 initial_regs = [0] * 32
79 initial_regs[1] = 0x8fffffff
80 with Program(lst, bigendian=False) as program:
81 sim = self.run_tst_program(program, initial_regs)
82 self.assertEqual(sim.gpr(3), SelectableInt(1, 64))
84 def test_case_rlwinm_2(self):
85 lst = ["rlwinm 3, 1, 1, 0, 30"]
86 initial_regs = [0] * 32
87 initial_regs[1] = 0xf1110001
88 with Program(lst, bigendian=False) as program:
89 sim = self.run_tst_program(program, initial_regs)
90 self.assertEqual(sim.gpr(3), SelectableInt(0xe2220002, 64))
92 def test_case_rlwinm_3(self):
93 lst = ["rlwinm 3, 1, 0, 16, 31"] # Clear high-order 16 bits
94 initial_regs = [0] * 32
95 initial_regs[1] = 0xebeb1888
96 with Program(lst, bigendian=False) as program:
97 sim = self.run_tst_program(program, initial_regs)
98 self.assertEqual(sim.gpr(3), SelectableInt(0x1888, 64))
100 def test_case_rlwimi_1(self):
101 lst = ["rlwimi 3, 1, 31, 0, 0"]
102 initial_regs = [0] * 32
103 initial_regs[1] = 0x1
104 initial_regs[3] = 0x7fffffff
105 with Program(lst, bigendian=False) as program:
106 sim = self.run_tst_program(program, initial_regs)
107 self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff, 64))
109 def test_case_rlwimi_2(self):
110 lst = ["rlwimi 3, 1, 16, 8, 15"]
111 initial_regs = [0] * 32
112 initial_regs[1] = 0xcc
113 initial_regs[3] = 0x7f00ffff
114 with Program(lst, bigendian=False) as program:
115 sim = self.run_tst_program(program, initial_regs)
116 self.assertEqual(sim.gpr(3), SelectableInt(0x7fccffff, 64))
118 def test_case_rlwnm_1(self):
119 lst = ["rlwnm 3, 1, 2, 0, 31"]
120 initial_regs = [0] * 32
121 initial_regs[1] = 0x111
123 with Program(lst, bigendian=False) as program:
124 sim = self.run_tst_program(program, initial_regs)
125 self.assertEqual(sim.gpr(3), SelectableInt(0x222, 64))
127 def test_case_rlwnm_2(self):
128 lst = ["rlwnm 3, 1, 2, 8, 11"]
129 initial_regs = [0] * 32
130 initial_regs[1] = 0xfebaacda
132 with Program(lst, bigendian=False) as program:
133 sim = self.run_tst_program(program, initial_regs)
134 self.assertEqual(sim.gpr(3), SelectableInt(0xd00000, 64))
136 def test_case_rldic_1(self):
137 lst = ["rldic 3, 1, 8, 31"] # Simple rotate and clear
138 initial_regs = [0] * 32
139 initial_regs[1] = 0x0100ffff00000111
140 with Program(lst, bigendian=False) as program:
141 sim = self.run_tst_program(program, initial_regs)
142 self.assertEqual(sim.gpr(3), SelectableInt(0x11100, 64))
144 def test_case_rldic_2(self):
145 lst = ["rldic 3, 1, 0, 51"] # No rotate and clear
146 initial_regs = [0] * 32
147 initial_regs[1] = 0x0100ffff00000fff
148 with Program(lst, bigendian=False) as program:
149 sim = self.run_tst_program(program, initial_regs)
150 self.assertEqual(sim.gpr(3), SelectableInt(0xfff, 64))
152 def test_case_rldicl_1(self):
153 lst = ["rldicl 3, 1, 8, 44"] # Simple rotate with left clear
154 initial_regs = [0] * 32
155 initial_regs[1] = 0x0100ffff00000111
156 with Program(lst, bigendian=False) as program:
157 sim = self.run_tst_program(program, initial_regs)
158 self.assertEqual(sim.gpr(3), SelectableInt(0x11101, 64))
160 def test_case_rldicl_2(self):
161 lst = ["rldicl 3, 1, 32, 47"] # Rotate right and clear
162 initial_regs = [0] * 32
163 initial_regs[1] = 0x1000dead0000111c
164 with Program(lst, bigendian=False) as program:
165 sim = self.run_tst_program(program, initial_regs)
166 self.assertEqual(sim.gpr(3), SelectableInt(0xdead, 64))
168 def test_case_rldicr_1(self):
169 lst = ["rldicr 3, 1, 16, 15"] # Simple rotate with right clear
170 initial_regs = [0] * 32
171 initial_regs[1] = 0x0100ffffe0000111
172 with Program(lst, bigendian=False) as program:
173 sim = self.run_tst_program(program, initial_regs)
174 self.assertEqual(sim.gpr(3), SelectableInt(0xffff000000000000, 64))
176 def test_case_rldicr_2(self):
177 lst = ["rldicr 3, 1, 32, 32"] # Rotate right and clear
178 initial_regs = [0] * 32
179 initial_regs[1] = 0x1000caef0000dead
180 with Program(lst, bigendian=False) as program:
181 sim = self.run_tst_program(program, initial_regs)
182 self.assertEqual(sim.gpr(3), SelectableInt(0xdead00000000, 64))
184 def test_case_regression_extswsli_1(self):
185 lst = [f"extswsli 3, 1, 31"]
186 initial_regs = [0] * 32
187 initial_regs[1] = 0x5678
188 with Program(lst, bigendian=False) as program:
189 sim = self.run_tst_program(program, initial_regs)
190 self.assertEqual(sim.gpr(3), SelectableInt(0x2b3c00000000, 64))
192 def test_case_regression_extswsli_2(self):
193 lst = [f"extswsli 3, 1, 7"]
194 initial_regs = [0] * 32
195 initial_regs[1] = 0x3ffffd7377f19fdd
196 with Program(lst, bigendian=False) as program:
197 sim = self.run_tst_program(program, initial_regs)
198 self.assertEqual(sim.gpr(3), SelectableInt(0x3bf8cfee80, 64))
200 def test_case_regression_extswsli_3(self):
201 lst = [f"extswsli 3, 1, 0"]
202 initial_regs = [0] * 32
203 initial_regs[1] = 0x0000010180122900
204 with Program(lst, bigendian=False) as program:
205 sim = self.run_tst_program(program, initial_regs)
206 self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff80122900, 64))
209 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_mem
=None):
210 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
)
214 def check_regs(self
, sim
, e
):
217 self
.assertEqual(sim
.gpr(i
), SelectableInt(e
.intregs
[i
], 64),
218 "int reg %d -> sim not equal to expected." % (i
))
220 self
.assertEqual(sim
.pc
.CIA
.value
, SelectableInt(e
.pc
, 64),
221 "pc -> sim not equal to expected.")
224 self
.assertEqual(sim
.crl
[7 - i
].get_range().value
,
225 SelectableInt(e
.crregs
[7-i
], 64),
226 "cr reg %d -> sim not equal to expected." % (i
))
228 self
.so
= sim
.spr
['XER'][XER_bits
['SO']].value
229 self
.ov
= sim
.spr
['XER'][XER_bits
['OV']].value
230 self
.ov32
= sim
.spr
['XER'][XER_bits
['OV32']].value
231 self
.ca
= sim
.spr
['XER'][XER_bits
['CA']].value
232 self
.ca32
= sim
.spr
['XER'][XER_bits
['CA32']].value
233 self
.ov
= self
.ov |
(self
.ov32
<< 1)
234 self
.ca
= self
.ca |
(self
.ca32
<< 1)
235 self
.assertEqual(self
.so
, SelectableInt(e
.so
, 64),
236 "so -> sim not equal to expected.")
237 self
.assertEqual(self
.ov
, SelectableInt(e
.ov
, 64),
238 "ov -> sim not equal to expected.")
239 self
.assertEqual(self
.ca
, SelectableInt(e
.ca
, 64),
240 "ca -> sim not equal to expected.")
243 if __name__
== "__main__":