1 from nmutil
.formaltest
import FHDLTestCase
3 from openpower
.decoder
.power_enums
import XER_bits
4 from openpower
.test
.state
import ExpectedState
, TestState
5 from openpower
.simulator
.program
import Program
6 from openpower
.decoder
.selectable_int
import SelectableInt
7 from openpower
.decoder
.isa
.test_runner
import run_tst
10 class DecoderTestCase(FHDLTestCase
):
12 def test_0_proof_regression_rlwnm(self
):
13 lst
= ["rlwnm 3, 1, 2, 16, 20"]
14 initial_regs
= [0] * 32
15 #initial_regs[1] =0x7ffdbffb91b906b9
16 initial_regs
[1] = 0x11faafff1111aa11
19 # set expected (intregs, pc, [crregs], so, ov, ca)
20 e
= ExpectedState(initial_regs
, 4)
22 with
Program(lst
, bigendian
=False) as program
:
23 # and here lies the rabbit hole...at least for me
24 sim
= self
.run_tst_program(program
, initial_regs
)
25 yield from self
.check_regs(sim
, e
)
27 def test_case_srw_1(self):
28 lst = ["sraw 3, 1, 2"]
29 initial_regs = [0] * 32
30 initial_regs[1] = 0x12345678
32 e = ExpectedState(initial_regs, 4, [0,0,0,0,0,0,0,0], 0, 0, 0)
33 e.intregs[3] = 0x123456
34 with Program(lst, bigendian=False) as program:
35 sim = self.run_tst_program(program, initial_regs)
36 self.check_regs(sim, e)
38 def test_case_srw_2(self):
39 lst = ["sraw 3, 1, 2"]
40 initial_regs = [0] * 32
41 initial_regs[1] = 0x82345678 # test the carry
43 with Program(lst, bigendian=False) as program:
44 sim = self.run_tst_program(program, initial_regs)
45 self.assertEqual(sim.gpr(3), SelectableInt(0xffffffffff823456, 64))
47 def test_case_sld_rb_too_big(self):
50 initial_regs = [0] * 32
51 initial_regs[1] = 0xffffffffffffffff
52 initial_regs[4] = 64 # too big, output should be zero
53 with Program(lst, bigendian=False) as program:
54 sim = self.run_tst_program(program, initial_regs)
55 self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
57 def test_case_sld_rb_is_zero(self):
59 initial_regs = [0] * 32
60 initial_regs[1] = 0x8000000000000000
61 initial_regs[4] = 0 # no shift; output should equal input
62 with Program(lst, bigendian=False) as program:
63 sim = self.run_tst_program(program, initial_regs)
64 self.assertEqual(sim.gpr(3), SelectableInt(initial_regs[1], 64))
66 def test_case_shift_once(self):
69 initial_regs = [0] * 32
70 initial_regs[1] = 0x80000000
71 initial_regs[2] = 0x40
72 initial_regs[4] = 0x00
73 with Program(lst, bigendian=False) as program:
74 sim = self.run_tst_program(program, initial_regs)
75 self.assertEqual(sim.gpr(1), SelectableInt(initial_regs[1], 64))
77 def test_case_rlwinm_1(self):
78 lst = ["rlwinm 3, 1, 1, 31, 31"] # Extracts sign bit
79 initial_regs = [0] * 32
80 initial_regs[1] = 0x8fffffff
81 with Program(lst, bigendian=False) as program:
82 sim = self.run_tst_program(program, initial_regs)
83 self.assertEqual(sim.gpr(3), SelectableInt(1, 64))
85 def test_case_rlwinm_2(self):
86 lst = ["rlwinm 3, 1, 1, 0, 30"]
87 initial_regs = [0] * 32
88 initial_regs[1] = 0xf1110001
89 with Program(lst, bigendian=False) as program:
90 sim = self.run_tst_program(program, initial_regs)
91 self.assertEqual(sim.gpr(3), SelectableInt(0xe2220002, 64))
93 def test_case_rlwinm_3(self):
94 lst = ["rlwinm 3, 1, 0, 16, 31"] # Clear high-order 16 bits
95 initial_regs = [0] * 32
96 initial_regs[1] = 0xebeb1888
97 with Program(lst, bigendian=False) as program:
98 sim = self.run_tst_program(program, initial_regs)
99 self.assertEqual(sim.gpr(3), SelectableInt(0x1888, 64))
101 def test_case_rlwimi_1(self):
102 lst = ["rlwimi 3, 1, 31, 0, 0"]
103 initial_regs = [0] * 32
104 initial_regs[1] = 0x1
105 initial_regs[3] = 0x7fffffff
106 with Program(lst, bigendian=False) as program:
107 sim = self.run_tst_program(program, initial_regs)
108 self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff, 64))
110 def test_case_rlwimi_2(self):
111 lst = ["rlwimi 3, 1, 16, 8, 15"]
112 initial_regs = [0] * 32
113 initial_regs[1] = 0xcc
114 initial_regs[3] = 0x7f00ffff
115 with Program(lst, bigendian=False) as program:
116 sim = self.run_tst_program(program, initial_regs)
117 self.assertEqual(sim.gpr(3), SelectableInt(0x7fccffff, 64))
119 def test_case_rlwnm_1(self):
120 lst = ["rlwnm 3, 1, 2, 0, 31"]
121 initial_regs = [0] * 32
122 initial_regs[1] = 0x111
124 with Program(lst, bigendian=False) as program:
125 sim = self.run_tst_program(program, initial_regs)
126 self.assertEqual(sim.gpr(3), SelectableInt(0x222, 64))
128 def test_case_rlwnm_2(self):
129 lst = ["rlwnm 3, 1, 2, 8, 11"]
130 initial_regs = [0] * 32
131 initial_regs[1] = 0xfebaacda
133 with Program(lst, bigendian=False) as program:
134 sim = self.run_tst_program(program, initial_regs)
135 self.assertEqual(sim.gpr(3), SelectableInt(0xd00000, 64))
137 def test_case_rldic_1(self):
138 lst = ["rldic 3, 1, 8, 31"] # Simple rotate and clear
139 initial_regs = [0] * 32
140 initial_regs[1] = 0x0100ffff00000111
141 with Program(lst, bigendian=False) as program:
142 sim = self.run_tst_program(program, initial_regs)
143 self.assertEqual(sim.gpr(3), SelectableInt(0x11100, 64))
145 def test_case_rldic_2(self):
146 lst = ["rldic 3, 1, 0, 51"] # No rotate and clear
147 initial_regs = [0] * 32
148 initial_regs[1] = 0x0100ffff00000fff
149 with Program(lst, bigendian=False) as program:
150 sim = self.run_tst_program(program, initial_regs)
151 self.assertEqual(sim.gpr(3), SelectableInt(0xfff, 64))
153 def test_case_rldicl_1(self):
154 lst = ["rldicl 3, 1, 8, 44"] # Simple rotate with left clear
155 initial_regs = [0] * 32
156 initial_regs[1] = 0x0100ffff00000111
157 with Program(lst, bigendian=False) as program:
158 sim = self.run_tst_program(program, initial_regs)
159 self.assertEqual(sim.gpr(3), SelectableInt(0x11101, 64))
161 def test_case_rldicl_2(self):
162 lst = ["rldicl 3, 1, 32, 47"] # Rotate right and clear
163 initial_regs = [0] * 32
164 initial_regs[1] = 0x1000dead0000111c
165 with Program(lst, bigendian=False) as program:
166 sim = self.run_tst_program(program, initial_regs)
167 self.assertEqual(sim.gpr(3), SelectableInt(0xdead, 64))
169 def test_case_rldicr_1(self):
170 lst = ["rldicr 3, 1, 16, 15"] # Simple rotate with right clear
171 initial_regs = [0] * 32
172 initial_regs[1] = 0x0100ffffe0000111
173 with Program(lst, bigendian=False) as program:
174 sim = self.run_tst_program(program, initial_regs)
175 self.assertEqual(sim.gpr(3), SelectableInt(0xffff000000000000, 64))
177 def test_case_rldicr_2(self):
178 lst = ["rldicr 3, 1, 32, 32"] # Rotate right and clear
179 initial_regs = [0] * 32
180 initial_regs[1] = 0x1000caef0000dead
181 with Program(lst, bigendian=False) as program:
182 sim = self.run_tst_program(program, initial_regs)
183 self.assertEqual(sim.gpr(3), SelectableInt(0xdead00000000, 64))
185 def test_case_regression_extswsli_1(self):
186 lst = [f"extswsli 3, 1, 31"]
187 initial_regs = [0] * 32
188 initial_regs[1] = 0x5678
189 with Program(lst, bigendian=False) as program:
190 sim = self.run_tst_program(program, initial_regs)
191 self.assertEqual(sim.gpr(3), SelectableInt(0x2b3c00000000, 64))
193 def test_case_regression_extswsli_2(self):
194 lst = [f"extswsli 3, 1, 7"]
195 initial_regs = [0] * 32
196 initial_regs[1] = 0x3ffffd7377f19fdd
197 with Program(lst, bigendian=False) as program:
198 sim = self.run_tst_program(program, initial_regs)
199 self.assertEqual(sim.gpr(3), SelectableInt(0x3bf8cfee80, 64))
201 def test_case_regression_extswsli_3(self):
202 lst = [f"extswsli 3, 1, 0"]
203 initial_regs = [0] * 32
204 initial_regs[1] = 0x0000010180122900
205 with Program(lst, bigendian=False) as program:
206 sim = self.run_tst_program(program, initial_regs)
207 self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff80122900, 64))
210 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_mem
=None):
211 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
)
216 def check_regs(self
, sim
, e
):
217 simstate
= yield from TestState("sim",sim
,self
)
218 yield from simstate
.compare(e
)
221 def check_regs(self, sim, e):
224 self.assertEqual(sim.gpr(i), SelectableInt(e.intregs[i], 64),
225 "int reg %d -> sim not equal to expected." % (i))
227 self.assertEqual(sim.pc.CIA.value, SelectableInt(e.pc, 64),
228 "pc -> sim not equal to expected.")
231 self.assertEqual(sim.crl[7 - i].get_range().value,
232 SelectableInt(e.crregs[7-i], 64),
233 "cr reg %d -> sim not equal to expected." % (i))
235 self.so = sim.spr['XER'][XER_bits['SO']].value
236 self.ov = sim.spr['XER'][XER_bits['OV']].value
237 self.ov32 = sim.spr['XER'][XER_bits['OV32']].value
238 self.ca = sim.spr['XER'][XER_bits['CA']].value
239 self.ca32 = sim.spr['XER'][XER_bits['CA32']].value
240 self.ov = self.ov | (self.ov32 << 1)
241 self.ca = self.ca | (self.ca32 << 1)
242 self.assertEqual(self.so, SelectableInt(e.so, 64),
243 "so -> sim not equal to expected.")
244 self.assertEqual(self.ov, SelectableInt(e.ov, 64),
245 "ov -> sim not equal to expected.")
246 self.assertEqual(self.ca, SelectableInt(e.ca, 64),
247 "ca -> sim not equal to expected.")
251 if __name__
== "__main__":