src/openpower/decoder/isa/test_caller_shift_rot.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller, inject
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.selectable_int import SelectableInt
  10 from openpower.decoder.orderedset import OrderedSet
  11 from openpower.decoder.isa.all import ISA
  12 from openpower.consts import PIb
  13
  14
  15 class Register:
  16     def __init__(self, num):
  17         self.num = num
  18
  19
  20 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
  21             initial_cr=0, mem=None):
  22     if initial_sprs is None:
  23         initial_sprs = {}
  24     m = Module()
  25     comb = m.d.comb
  26     instruction = Signal(32)
  27
  28     pdecode = create_pdecode()
  29
  30     gen = list(generator.generate_instructions())
  31     insncode = generator.assembly.splitlines()
  32     instructions = list(zip(gen, insncode))
  33
  34     m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  35     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
  36                     initial_insns=gen, respect_pc=True,
  37                     initial_svstate=svstate,
  38                     initial_mem=mem,
  39                     disassembly=insncode,
  40                     bigendian=0,
  41                     mmu=mmu)
  42     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  43     sim = Simulator(m)
  44
  45     def process():
  46
  47         yield pdecode2.dec.bigendian.eq(0)  # little / big?
  48         pc = simulator.pc.CIA.value
  49         index = pc // 4
  50         while index < len(instructions):
  51             print("instr pc", pc)
  52             try:
  53                 yield from simulator.setup_one()
  54             except KeyError:  # indicates instruction not in imem: stop
  55                 break
  56             yield Settle()
  57
  58             ins, code = instructions[index]
  59             print("    0x{:X}".format(ins & 0xffffffff))
  60             opname = code.split(' ')[0]
  61             print(code, opname)
  62
  63             # ask the decoder to decode this binary data (endian'd)
  64             yield from simulator.execute_one()
  65             pc = simulator.pc.CIA.value
  66             index = pc // 4
  67
  68     sim.add_process(process)
  69     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  70                        traces=[]):
  71         sim.run()
  72     return simulator
  73
  74
  75 class DecoderTestCase(FHDLTestCase):
  76
  77     def test_0_proof_regression_rlwnm(self):
  78         lst = ["rlwnm 3, 1, 2, 16, 20"]
  79         initial_regs = [0] * 32
  80         #initial_regs[1] =0x7ffdbffb91b906b9
  81         initial_regs[1] = 0x11faafff1111aa11
  82         #initial_regs[2] = 31
  83         initial_regs[2] = 11
  84         with Program(lst, bigendian=False) as program:
  85             sim = self.run_tst_program(program, initial_regs)
  86
  87     def test_case_srw_1(self):
  88         lst = ["sraw 3, 1, 2"]
  89         initial_regs = [0] * 32
  90         initial_regs[1] = 0x12345678
  91         initial_regs[2] = 8
  92         with Program(lst, bigendian=False) as program:
  93             sim = self.run_tst_program(program, initial_regs)
  94             self.assertEqual(sim.gpr(3), SelectableInt(0x123456, 64))
  95
  96     def test_case_srw_1(self):
  97         lst = ["sraw 3, 1, 2"]
  98         initial_regs = [0] * 32
  99         initial_regs[1] = 0x82345678  # test the carry
 100         initial_regs[2] = 8
 101         with Program(lst, bigendian=False) as program:
 102             sim = self.run_tst_program(program, initial_regs)
 103             self.assertEqual(sim.gpr(3), SelectableInt(0xffffffffff823456, 64))
 104
 105     def test_case_sld_rb_too_big(self):
 106         lst = ["sld 3, 1, 4",
 107                ]
 108         initial_regs = [0] * 32
 109         initial_regs[1] = 0xffffffffffffffff
 110         initial_regs[4] = 64  # too big, output should be zero
 111         with Program(lst, bigendian=False) as program:
 112             sim = self.run_tst_program(program, initial_regs)
 113             self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
 114
 115     def test_case_sld_rb_is_zero(self):
 116         lst = ["sld 3, 1, 4"]
 117         initial_regs = [0] * 32
 118         initial_regs[1] = 0x8000000000000000
 119         initial_regs[4] = 0  # no shift; output should equal input
 120         with Program(lst, bigendian=False) as program:
 121             sim = self.run_tst_program(program, initial_regs)
 122             self.assertEqual(sim.gpr(3), SelectableInt(initial_regs[1], 64))
 123
 124     def test_case_shift_once(self):
 125         lst = ["slw 3, 1, 4",
 126                "slw 3, 1, 2"]
 127         initial_regs = [0] * 32
 128         initial_regs[1] = 0x80000000
 129         initial_regs[2] = 0x40
 130         initial_regs[4] = 0x00
 131         with Program(lst, bigendian=False) as program:
 132             sim = self.run_tst_program(program, initial_regs)
 133             self.assertEqual(sim.gpr(1), SelectableInt(initial_regs[1], 64))
 134
 135     def test_case_rlwinm_1(self):
 136         lst = ["rlwinm 3, 1, 1, 31, 31"]  # Extracts sign bit
 137         initial_regs = [0] * 32
 138         initial_regs[1] = 0x8fffffff
 139         with Program(lst, bigendian=False) as program:
 140             sim = self.run_tst_program(program, initial_regs)
 141             self.assertEqual(sim.gpr(3), SelectableInt(1, 64))
 142
 143     def test_case_rlwinm_2(self):
 144         lst = ["rlwinm 3, 1, 1, 0, 30"]
 145         initial_regs = [0] * 32
 146         initial_regs[1] = 0xf1110001
 147         with Program(lst, bigendian=False) as program:
 148             sim = self.run_tst_program(program, initial_regs)
 149             self.assertEqual(sim.gpr(3), SelectableInt(0xe2220002, 64))
 150
 151     def test_case_rlwinm_3(self):
 152         lst = ["rlwinm 3, 1, 0, 16, 31"]  # Clear high-order 16 bits
 153         initial_regs = [0] * 32
 154         initial_regs[1] = 0xebeb1888
 155         with Program(lst, bigendian=False) as program:
 156             sim = self.run_tst_program(program, initial_regs)
 157             self.assertEqual(sim.gpr(3), SelectableInt(0x1888, 64))
 158
 159     def test_case_rlwimi_1(self):
 160         lst = ["rlwimi 3, 1, 31, 0, 0"]
 161         initial_regs = [0] * 32
 162         initial_regs[1] = 0x1
 163         initial_regs[3] = 0x7fffffff
 164         with Program(lst, bigendian=False) as program:
 165             sim = self.run_tst_program(program, initial_regs)
 166             self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff, 64))
 167
 168     def test_case_rlwimi_2(self):
 169         lst = ["rlwimi 3, 1, 16, 8, 15"]
 170         initial_regs = [0] * 32
 171         initial_regs[1] = 0xcc
 172         initial_regs[3] = 0x7f00ffff
 173         with Program(lst, bigendian=False) as program:
 174             sim = self.run_tst_program(program, initial_regs)
 175             self.assertEqual(sim.gpr(3), SelectableInt(0x7fccffff, 64))
 176
 177     def test_case_rlwnm_1(self):
 178         lst = ["rlwnm 3, 1, 2, 0, 31"]
 179         initial_regs = [0] * 32
 180         initial_regs[1] = 0x111
 181         initial_regs[2] = 1
 182         with Program(lst, bigendian=False) as program:
 183             sim = self.run_tst_program(program, initial_regs)
 184             self.assertEqual(sim.gpr(3), SelectableInt(0x222, 64))
 185
 186     def test_case_rlwnm_2(self):
 187         lst = ["rlwnm 3, 1, 2, 8, 11"]
 188         initial_regs = [0] * 32
 189         initial_regs[1] = 0xfebaacda
 190         initial_regs[2] = 16
 191         with Program(lst, bigendian=False) as program:
 192             sim = self.run_tst_program(program, initial_regs)
 193             self.assertEqual(sim.gpr(3), SelectableInt(0xd00000, 64))
 194
 195     def test_case_rldic_1(self):
 196         lst = ["rldic 3, 1, 8, 31"]  # Simple rotate and clear
 197         initial_regs = [0] * 32
 198         initial_regs[1] = 0x0100ffff00000111
 199         with Program(lst, bigendian=False) as program:
 200             sim = self.run_tst_program(program, initial_regs)
 201             self.assertEqual(sim.gpr(3), SelectableInt(0x11100, 64))
 202
 203     def test_case_rldic_2(self):
 204         lst = ["rldic 3, 1, 0, 51"]  # No rotate and clear
 205         initial_regs = [0] * 32
 206         initial_regs[1] = 0x0100ffff00000fff
 207         with Program(lst, bigendian=False) as program:
 208             sim = self.run_tst_program(program, initial_regs)
 209             self.assertEqual(sim.gpr(3), SelectableInt(0xfff, 64))
 210
 211     def test_case_rldicl_1(self):
 212         lst = ["rldicl 3, 1, 8, 44"]  # Simple rotate with left clear
 213         initial_regs = [0] * 32
 214         initial_regs[1] = 0x0100ffff00000111
 215         with Program(lst, bigendian=False) as program:
 216             sim = self.run_tst_program(program, initial_regs)
 217             self.assertEqual(sim.gpr(3), SelectableInt(0x11101, 64))
 218
 219     def test_case_rldicl_2(self):
 220         lst = ["rldicl 3, 1, 32, 47"]  # Rotate right and clear
 221         initial_regs = [0] * 32
 222         initial_regs[1] = 0x1000dead0000111c
 223         with Program(lst, bigendian=False) as program:
 224             sim = self.run_tst_program(program, initial_regs)
 225             self.assertEqual(sim.gpr(3), SelectableInt(0xdead, 64))
 226
 227     def test_case_rldicr_1(self):
 228         lst = ["rldicr 3, 1, 16, 15"]  # Simple rotate with right clear
 229         initial_regs = [0] * 32
 230         initial_regs[1] = 0x0100ffffe0000111
 231         with Program(lst, bigendian=False) as program:
 232             sim = self.run_tst_program(program, initial_regs)
 233             self.assertEqual(sim.gpr(3), SelectableInt(0xffff000000000000, 64))
 234
 235     def test_case_rldicr_2(self):
 236         lst = ["rldicr 3, 1, 32, 32"]  # Rotate right and clear
 237         initial_regs = [0] * 32
 238         initial_regs[1] = 0x1000caef0000dead
 239         with Program(lst, bigendian=False) as program:
 240             sim = self.run_tst_program(program, initial_regs)
 241             self.assertEqual(sim.gpr(3), SelectableInt(0xdead00000000, 64))
 242
 243     def test_case_regression_extswsli_1(self):
 244         lst = [f"extswsli 3, 1, 31"]
 245         initial_regs = [0] * 32
 246         initial_regs[1] = 0x5678
 247         with Program(lst, bigendian=False) as program:
 248             sim = self.run_tst_program(program, initial_regs)
 249             self.assertEqual(sim.gpr(3), SelectableInt(0x2b3c00000000, 64))
 250
 251     def test_case_regression_extswsli_2(self):
 252         lst = [f"extswsli 3, 1, 7"]
 253         initial_regs = [0] * 32
 254         initial_regs[1] = 0x3ffffd7377f19fdd
 255         with Program(lst, bigendian=False) as program:
 256             sim = self.run_tst_program(program, initial_regs)
 257             self.assertEqual(sim.gpr(3), SelectableInt(0x3bf8cfee80, 64))
 258
 259     def test_case_regression_extswsli_3(self):
 260         lst = [f"extswsli 3, 1, 0"]
 261         initial_regs = [0] * 32
 262         initial_regs[1] = 0x0000010180122900
 263         with Program(lst, bigendian=False) as program:
 264             sim = self.run_tst_program(program, initial_regs)
 265             self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff80122900, 64))
 266
 267     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None):
 268         simulator = run_tst(prog, initial_regs, mem=initial_mem)
 269         simulator.gpr.dump()
 270         return simulator
 271
 272
 273 if __name__ == "__main__":
 274     unittest.main()