1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
19 class DecoderTestCase(FHDLTestCase
):
21 def _check_regs(self
, sim
, expected
):
23 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
25 def test_sv_load_store(self
):
26 """>>> lst = ["addi 1, 0, 0x0010",
33 lst
= SVP64Asm(["addi 1, 0, 0x0010",
38 "sv.lwz 9.v, 0(1.v)"])
41 # SVSTATE (in this case, VL=2)
42 svstate
= SVP64State()
43 svstate
.vl
[0:7] = 2 # VL
44 svstate
.maxvl
[0:7] = 2 # MAXVL
45 print ("SVSTATE", bin(svstate
.spr
.asint()))
47 with
Program(lst
, bigendian
=False) as program
:
48 sim
= self
.run_tst_program(program
, svstate
=svstate
)
50 self
.assertEqual(sim
.gpr(9), SelectableInt(0x1234, 64))
51 self
.assertEqual(sim
.gpr(10), SelectableInt(0x1235, 64))
53 def test_sv_add(self
):
54 """>>> lst = ['sv.add 1.v, 5.v, 9.v'
57 * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
58 * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
60 isa
= SVP64Asm(['sv.add 1.v, 5.v, 9.v'
63 print ("listing", lst
)
65 # initial values in GPR regfile
66 initial_regs
= [0] * 32
67 initial_regs
[5] = 0x4321
68 initial_regs
[9] = 0x1234
69 initial_regs
[10] = 0x1111
70 initial_regs
[6] = 0x2223
71 # SVSTATE (in this case, VL=2)
72 svstate
= SVP64State()
73 svstate
.vl
[0:7] = 2 # VL
74 svstate
.maxvl
[0:7] = 2 # MAXVL
75 print ("SVSTATE", bin(svstate
.spr
.asint()))
76 # copy before running, then compute answers
77 expected_regs
= deepcopy(initial_regs
)
78 expected_regs
[1] = initial_regs
[5] + initial_regs
[9] # 0x5555
79 expected_regs
[2] = initial_regs
[6] + initial_regs
[10] # 0x3334
81 with
Program(lst
, bigendian
=False) as program
:
82 sim
= self
.run_tst_program(program
, initial_regs
, svstate
)
83 self
._check
_regs
(sim
, expected_regs
)
85 def test_sv_add_2(self
):
86 """>>> lst = ['sv.add 1, 5.v, 9.v' ]
88 * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
89 * r1 is scalar so ENDS EARLY
91 isa
= SVP64Asm(['sv.add 1, 5.v, 9.v'
94 print ("listing", lst
)
96 # initial values in GPR regfile
97 initial_regs
= [0] * 32
98 initial_regs
[9] = 0x1234
99 initial_regs
[10] = 0x1111
100 initial_regs
[5] = 0x4321
101 initial_regs
[6] = 0x2223
102 # SVSTATE (in this case, VL=2)
103 svstate
= SVP64State()
104 svstate
.vl
[0:7] = 2 # VL
105 svstate
.maxvl
[0:7] = 2 # MAXVL
106 print ("SVSTATE", bin(svstate
.spr
.asint()))
107 # copy before running
108 expected_regs
= deepcopy(initial_regs
)
109 expected_regs
[1] = initial_regs
[5] + initial_regs
[9] # 0x5555
111 with
Program(lst
, bigendian
=False) as program
:
112 sim
= self
.run_tst_program(program
, initial_regs
, svstate
)
113 self
._check
_regs
(sim
, expected_regs
)
115 def test_sv_add_3(self
):
116 """>>> lst = ['sv.add 1.v, 5, 9.v' ]
119 * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
120 * 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
122 isa
= SVP64Asm(['sv.add 1.v, 5, 9.v'
125 print ("listing", lst
)
127 # initial values in GPR regfile
128 initial_regs
= [0] * 32
129 initial_regs
[9] = 0x1234
130 initial_regs
[10] = 0x1111
131 initial_regs
[5] = 0x4321
132 initial_regs
[6] = 0x2223
133 # SVSTATE (in this case, VL=2)
134 svstate
= SVP64State()
135 svstate
.vl
[0:7] = 2 # VL
136 svstate
.maxvl
[0:7] = 2 # MAXVL
137 print ("SVSTATE", bin(svstate
.spr
.asint()))
138 # copy before running
139 expected_regs
= deepcopy(initial_regs
)
140 expected_regs
[1] = initial_regs
[5] + initial_regs
[9] # 0x5555
141 expected_regs
[2] = initial_regs
[5] + initial_regs
[10] # 0x5432
143 with
Program(lst
, bigendian
=False) as program
:
144 sim
= self
.run_tst_program(program
, initial_regs
, svstate
)
145 self
._check
_regs
(sim
, expected_regs
)
147 def test_sv_add_vl_0(self
):
148 """>>> lst = ['sv.add 1, 5.v, 9.v'
151 * none because VL is zero
153 isa
= SVP64Asm(['sv.add 1, 5.v, 9.v'
156 print ("listing", lst
)
158 # initial values in GPR regfile
159 initial_regs
= [0] * 32
160 initial_regs
[9] = 0x1234
161 initial_regs
[10] = 0x1111
162 initial_regs
[5] = 0x4321
163 initial_regs
[6] = 0x2223
164 # SVSTATE (in this case, VL=0)
165 svstate
= SVP64State()
166 svstate
.vl
[0:7] = 0 # VL
167 svstate
.maxvl
[0:7] = 0 # MAXVL
168 print ("SVSTATE", bin(svstate
.spr
.asint()))
169 # copy before running
170 expected_regs
= deepcopy(initial_regs
)
172 with
Program(lst
, bigendian
=False) as program
:
173 sim
= self
.run_tst_program(program
, initial_regs
, svstate
)
174 self
._check
_regs
(sim
, expected_regs
)
176 def test_sv_add_cr(self
):
177 """>>> lst = ['sv.add. 1.v, 5.v, 9.v'
180 adds when Rc=1: TODO CRs higher up
181 * 1 = 5 + 9 => 0 = -1+1 CR0=0b100
182 * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
184 isa
= SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
187 print ("listing", lst
)
189 # initial values in GPR regfile
190 initial_regs
= [0] * 32
191 initial_regs
[9] = 0xffffffffffffffff
192 initial_regs
[10] = 0x1111
193 initial_regs
[5] = 0x1
194 initial_regs
[6] = 0x2223
195 # SVSTATE (in this case, VL=2)
196 svstate
= SVP64State()
197 svstate
.vl
[0:7] = 2 # VL
198 svstate
.maxvl
[0:7] = 2 # MAXVL
199 print ("SVSTATE", bin(svstate
.spr
.asint()))
200 # copy before running
201 expected_regs
= deepcopy(initial_regs
)
202 expected_regs
[1] = initial_regs
[5] + initial_regs
[9] # 0x0
203 expected_regs
[2] = initial_regs
[6] + initial_regs
[10] # 0x3334
205 with
Program(lst
, bigendian
=False) as program
:
206 sim
= self
.run_tst_program(program
, initial_regs
, svstate
)
207 # XXX TODO, these need to move to higher range (offset)
208 cr0_idx
= SVP64CROffs
.CR0
209 cr1_idx
= SVP64CROffs
.CR1
210 CR0
= sim
.crl
[cr0_idx
].get_range().value
211 CR1
= sim
.crl
[cr1_idx
].get_range().value
214 self
._check
_regs
(sim
, expected_regs
)
215 self
.assertEqual(CR0
, SelectableInt(2, 4))
216 self
.assertEqual(CR1
, SelectableInt(4, 4))
218 def run_tst_program(self
, prog
, initial_regs
=None,
220 if initial_regs
is None:
221 initial_regs
= [0] * 32
222 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
)
227 if __name__
== "__main__":