src/openpower/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_sv_load_store(self):
  25         """>>> lst = ["addi 1, 0, 0x0010",
  26                         "addi 2, 0, 0x0008",
  27                         "addi 5, 0, 0x1234",
  28                         "addi 6, 0, 0x1235",
  29                         "sv.stw 5.v, 0(1.v)",
  30                         "sv.lwz 9.v, 0(1.v)"]
  31         """
  32         lst = SVP64Asm(["addi 1, 0, 0x0010",
  33                         "addi 2, 0, 0x0008",
  34                         "addi 5, 0, 0x1234",
  35                         "addi 6, 0, 0x1235",
  36                         "sv.stw 5.v, 0(1.v)",
  37                         "sv.lwz 9.v, 0(1.v)"])
  38         lst = list(lst)
  39
  40         # SVSTATE (in this case, VL=2)
  41         svstate = SVP64State()
  42         svstate.vl[0:7] = 2 # VL
  43         svstate.maxvl[0:7] = 2 # MAXVL
  44         print ("SVSTATE", bin(svstate.spr.asint()))
  45
  46         with Program(lst, bigendian=False) as program:
  47             sim = self.run_tst_program(program, svstate=svstate)
  48             print(sim.gpr(1))
  49             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  50             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  51
  52     def test_sv_add(self):
  53         """>>> lst = ['sv.add 1.v, 5.v, 9.v'
  54                        ]
  55         adds:
  56             * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  57             * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  58         """
  59         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
  60                        ])
  61         lst = list(isa)
  62         print ("listing", lst)
  63
  64         # initial values in GPR regfile
  65         initial_regs = [0] * 32
  66         initial_regs[5] = 0x4321
  67         initial_regs[9] = 0x1234
  68         initial_regs[10] = 0x1111
  69         initial_regs[6] = 0x2223
  70         # SVSTATE (in this case, VL=2)
  71         svstate = SVP64State()
  72         svstate.vl[0:7] = 2 # VL
  73         svstate.maxvl[0:7] = 2 # MAXVL
  74         print ("SVSTATE", bin(svstate.spr.asint()))
  75         # copy before running, then compute answers
  76         expected_regs = deepcopy(initial_regs)
  77         expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x5555
  78         expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334
  79
  80         with Program(lst, bigendian=False) as program:
  81             sim = self.run_tst_program(program, initial_regs, svstate)
  82             self._check_regs(sim, expected_regs)
  83
  84     def test_sv_add_2(self):
  85         """>>> lst = ['sv.add 1, 5.v, 9.v' ]
  86         adds:
  87             * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  88             * r1 is scalar so ENDS EARLY
  89         """
  90         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
  91                        ])
  92         lst = list(isa)
  93         print ("listing", lst)
  94
  95         # initial values in GPR regfile
  96         initial_regs = [0] * 32
  97         initial_regs[9] = 0x1234
  98         initial_regs[10] = 0x1111
  99         initial_regs[5] = 0x4321
 100         initial_regs[6] = 0x2223
 101         # SVSTATE (in this case, VL=2)
 102         svstate = SVP64State()
 103         svstate.vl[0:7] = 2 # VL
 104         svstate.maxvl[0:7] = 2 # MAXVL
 105         print ("SVSTATE", bin(svstate.spr.asint()))
 106         # copy before running
 107         expected_regs = deepcopy(initial_regs)
 108         expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555
 109
 110         with Program(lst, bigendian=False) as program:
 111             sim = self.run_tst_program(program, initial_regs, svstate)
 112             self._check_regs(sim, expected_regs)
 113
 114     def test_sv_add_3(self):
 115         """>>> lst = ['sv.add 1.v, 5, 9.v' ]
 116
 117         adds:
 118             * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 119             * 2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 120         """
 121         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
 122                        ])
 123         lst = list(isa)
 124         print ("listing", lst)
 125
 126         # initial values in GPR regfile
 127         initial_regs = [0] * 32
 128         initial_regs[9] = 0x1234
 129         initial_regs[10] = 0x1111
 130         initial_regs[5] = 0x4321
 131         initial_regs[6] = 0x2223
 132         # SVSTATE (in this case, VL=2)
 133         svstate = SVP64State()
 134         svstate.vl[0:7] = 2 # VL
 135         svstate.maxvl[0:7] = 2 # MAXVL
 136         print ("SVSTATE", bin(svstate.spr.asint()))
 137         # copy before running
 138         expected_regs = deepcopy(initial_regs)
 139         expected_regs[1] = initial_regs[5] + initial_regs[9]   # 0x5555
 140         expected_regs[2] = initial_regs[5] + initial_regs[10]  # 0x5432
 141
 142         with Program(lst, bigendian=False) as program:
 143             sim = self.run_tst_program(program, initial_regs, svstate)
 144             self._check_regs(sim, expected_regs)
 145
 146     def test_sv_add_vl_0(self):
 147         """>>> lst = ['sv.add 1, 5.v, 9.v'
 148                        ]
 149         adds:
 150             * none because VL is zero
 151         """
 152         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
 153                        ])
 154         lst = list(isa)
 155         print ("listing", lst)
 156
 157         # initial values in GPR regfile
 158         initial_regs = [0] * 32
 159         initial_regs[9] = 0x1234
 160         initial_regs[10] = 0x1111
 161         initial_regs[5] = 0x4321
 162         initial_regs[6] = 0x2223
 163         # SVSTATE (in this case, VL=0)
 164         svstate = SVP64State()
 165         svstate.vl[0:7] = 0 # VL
 166         svstate.maxvl[0:7] = 0 # MAXVL
 167         print ("SVSTATE", bin(svstate.spr.asint()))
 168         # copy before running
 169         expected_regs = deepcopy(initial_regs)
 170
 171         with Program(lst, bigendian=False) as program:
 172             sim = self.run_tst_program(program, initial_regs, svstate)
 173             self._check_regs(sim, expected_regs)
 174
 175     def test_sv_add_cr(self):
 176         """>>> lst = ['sv.add. 1.v, 5.v, 9.v'
 177                        ]
 178
 179         adds when Rc=1:                               TODO CRs higher up
 180             * 1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 181             * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 182         """
 183         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
 184                        ])
 185         lst = list(isa)
 186         print ("listing", lst)
 187
 188         # initial values in GPR regfile
 189         initial_regs = [0] * 32
 190         initial_regs[9] = 0xffffffffffffffff
 191         initial_regs[10] = 0x1111
 192         initial_regs[5] = 0x1
 193         initial_regs[6] = 0x2223
 194         # SVSTATE (in this case, VL=2)
 195         svstate = SVP64State()
 196         svstate.vl[0:7] = 2 # VL
 197         svstate.maxvl[0:7] = 2 # MAXVL
 198         print ("SVSTATE", bin(svstate.spr.asint()))
 199         # copy before running
 200         expected_regs = deepcopy(initial_regs)
 201         expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x0
 202         expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334
 203
 204         with Program(lst, bigendian=False) as program:
 205             sim = self.run_tst_program(program, initial_regs, svstate)
 206             # XXX TODO, these need to move to higher range (offset)
 207             cr0_idx = SVP64CROffs.CR0
 208             cr1_idx = SVP64CROffs.CR1
 209             CR0 = sim.crl[cr0_idx].get_range().value
 210             CR1 = sim.crl[cr1_idx].get_range().value
 211             print ("CR0", CR0)
 212             print ("CR1", CR1)
 213             self._check_regs(sim, expected_regs)
 214             self.assertEqual(CR0, SelectableInt(2, 4))
 215             self.assertEqual(CR1, SelectableInt(4, 4))
 216
 217     def run_tst_program(self, prog, initial_regs=None,
 218                               svstate=None):
 219         if initial_regs is None:
 220             initial_regs = [0] * 32
 221         simulator = run_tst(prog, initial_regs, svstate=svstate)
 222         simulator.gpr.dump()
 223         return simulator
 224
 225
 226 if __name__ == "__main__":
 227     unittest.main()