src/openpower/decoder/isa/test_caller_svp64.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.consts import SVP64CROffs
   6 from openpower.decoder.isa.caller import SVP64State
   7 from openpower.decoder.isa.test_caller import run_tst
   8 from openpower.decoder.selectable_int import SelectableInt
   9 from openpower.simulator.program import Program
  10 from openpower.insndb.asm import SVP64Asm
  11
  12
  13 class DecoderTestCase(FHDLTestCase):
  14
  15     def _check_regs(self, sim, expected):
  16         for i in range(32):
  17             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  18
  19     def test_sv_load_store(self):
  20         """>>> lst = ["addi 16, 0, 0x0010",
  21                         "addi 17, 0, 0x0008",
  22                         "addi 4, 0, 0x1234",
  23                         "addi 5, 0, 0x1235",
  24                         "sv.stw *4, 0(*16)",
  25                         "sv.lwz *8, 0(*16)"]
  26         """
  27         lst = SVP64Asm(["addi 16, 0, 0x0010",
  28                         "addi 17, 0, 0x0008",
  29                         "addi 4, 0, 0x1234",
  30                         "addi 5, 0, 0x1235",
  31                         "sv.stw *4, 0(*16)",
  32                         "sv.lwz *8, 0(*16)"])
  33         lst = list(lst)
  34
  35         # SVSTATE (in this case, VL=2)
  36         svstate = SVP64State()
  37         svstate.vl = 2  # VL
  38         svstate.maxvl = 2  # MAXVL
  39         print("SVSTATE", bin(svstate.asint()))
  40
  41         with Program(lst, bigendian=False) as program:
  42             sim = self.run_tst_program(program, svstate=svstate)
  43             print(sim.gpr(1))
  44             self.assertEqual(sim.gpr(8), SelectableInt(0x1234, 64))
  45             self.assertEqual(sim.gpr(9), SelectableInt(0x1235, 64))
  46
  47     def test_sv_add(self):
  48         """>>> lst = ['sv.add *1, *5, *9'
  49                        ]
  50         adds:
  51             * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  52             * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  53         """
  54         isa = SVP64Asm(['sv.add *1, *5, *9'
  55                         ])
  56         lst = list(isa)
  57         print("listing", lst)
  58
  59         # initial values in GPR regfile
  60         initial_regs = [0] * 32
  61         initial_regs[5] = 0x4321
  62         initial_regs[9] = 0x1234
  63         initial_regs[10] = 0x1111
  64         initial_regs[6] = 0x2223
  65         # SVSTATE (in this case, VL=2)
  66         svstate = SVP64State()
  67         svstate.vl = 2  # VL
  68         svstate.maxvl = 2  # MAXVL
  69         print("SVSTATE", bin(svstate.asint()))
  70         # copy before running, then compute answers
  71         expected_regs = deepcopy(initial_regs)
  72         expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x5555
  73         expected_regs[2] = initial_regs[6] + initial_regs[10]  # 0x3334
  74
  75         with Program(lst, bigendian=False) as program:
  76             sim = self.run_tst_program(program, initial_regs, svstate)
  77             self._check_regs(sim, expected_regs)
  78
  79     def test_sv_add_2(self):
  80         """>>> lst = ['sv.add 1, *5, *9' ]
  81         adds:
  82             * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  83             * r1 is scalar so ENDS EARLY
  84         """
  85         isa = SVP64Asm(['sv.add 1, *5, *9'
  86                         ])
  87         lst = list(isa)
  88         print("listing", lst)
  89
  90         # initial values in GPR regfile
  91         initial_regs = [0] * 32
  92         initial_regs[9] = 0x1234
  93         initial_regs[10] = 0x1111
  94         initial_regs[5] = 0x4321
  95         initial_regs[6] = 0x2223
  96         # SVSTATE (in this case, VL=2)
  97         svstate = SVP64State()
  98         svstate.vl = 2  # VL
  99         svstate.maxvl = 2  # MAXVL
 100         print("SVSTATE", bin(svstate.asint()))
 101         # copy before running
 102         expected_regs = deepcopy(initial_regs)
 103         expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x5555
 104
 105         with Program(lst, bigendian=False) as program:
 106             sim = self.run_tst_program(program, initial_regs, svstate)
 107             self._check_regs(sim, expected_regs)
 108
 109     def test_sv_add_3(self):
 110         """>>> lst = ['sv.add *1, 5, *9' ]
 111
 112         adds:
 113             * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 114             * 2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 115         """
 116         isa = SVP64Asm(['sv.add *1, 5, *9'
 117                         ])
 118         lst = list(isa)
 119         print("listing", lst)
 120
 121         # initial values in GPR regfile
 122         initial_regs = [0] * 32
 123         initial_regs[9] = 0x1234
 124         initial_regs[10] = 0x1111
 125         initial_regs[5] = 0x4321
 126         initial_regs[6] = 0x2223
 127         # SVSTATE (in this case, VL=2)
 128         svstate = SVP64State()
 129         svstate.vl = 2  # VL
 130         svstate.maxvl = 2  # MAXVL
 131         print("SVSTATE", bin(svstate.asint()))
 132         # copy before running
 133         expected_regs = deepcopy(initial_regs)
 134         expected_regs[1] = initial_regs[5] + initial_regs[9]   # 0x5555
 135         expected_regs[2] = initial_regs[5] + initial_regs[10]  # 0x5432
 136
 137         with Program(lst, bigendian=False) as program:
 138             sim = self.run_tst_program(program, initial_regs, svstate)
 139             self._check_regs(sim, expected_regs)
 140
 141     def test_sv_add_vl_0(self):
 142         """>>> lst = ['sv.add 1, *5, *9'
 143                        ]
 144         adds:
 145             * none because VL is zero
 146         """
 147         isa = SVP64Asm(['sv.add 1, *5, *9'
 148                         ])
 149         lst = list(isa)
 150         print("listing", lst)
 151
 152         # initial values in GPR regfile
 153         initial_regs = [0] * 32
 154         initial_regs[9] = 0x1234
 155         initial_regs[10] = 0x1111
 156         initial_regs[5] = 0x4321
 157         initial_regs[6] = 0x2223
 158         # SVSTATE (in this case, VL=0)
 159         svstate = SVP64State()
 160         svstate.vl = 0  # VL
 161         svstate.maxvl = 0  # MAXVL
 162         print("SVSTATE", bin(svstate.asint()))
 163         # copy before running
 164         expected_regs = deepcopy(initial_regs)
 165
 166         with Program(lst, bigendian=False) as program:
 167             sim = self.run_tst_program(program, initial_regs, svstate)
 168             self._check_regs(sim, expected_regs)
 169
 170     def test_sv_add_cr(self):
 171         """>>> lst = ['sv.add. *1, *5, *9'
 172                        ]
 173
 174         adds when Rc=1:                               TODO CRs higher up
 175             * 1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 176             * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 177         """
 178         isa = SVP64Asm(['sv.add. *1, *5, *9'
 179                         ])
 180         lst = list(isa)
 181         print("listing", lst)
 182
 183         # initial values in GPR regfile
 184         initial_regs = [0] * 32
 185         initial_regs[9] = 0xffffffffffffffff
 186         initial_regs[10] = 0x1111
 187         initial_regs[5] = 0x1
 188         initial_regs[6] = 0x2223
 189         # SVSTATE (in this case, VL=2)
 190         svstate = SVP64State()
 191         svstate.vl = 2  # VL
 192         svstate.maxvl = 2  # MAXVL
 193         print("SVSTATE", bin(svstate.asint()))
 194         # copy before running
 195         expected_regs = deepcopy(initial_regs)
 196         expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x0
 197         expected_regs[2] = initial_regs[6] + initial_regs[10]  # 0x3334
 198
 199         with Program(lst, bigendian=False) as program:
 200             sim = self.run_tst_program(program, initial_regs, svstate)
 201             # XXX TODO, these need to move to higher range (offset)
 202             cr0_idx = SVP64CROffs.CR0
 203             cr1_idx = SVP64CROffs.CR1
 204             CR0 = sim.crl[cr0_idx].get_range().value
 205             CR1 = sim.crl[cr1_idx].get_range().value
 206             print("CR0", CR0)
 207             print("CR1", CR1)
 208             self._check_regs(sim, expected_regs)
 209             self.assertEqual(CR0, SelectableInt(2, 4))
 210             self.assertEqual(CR1, SelectableInt(4, 4))
 211
 212     def run_tst_program(self, prog, initial_regs=None,
 213                         svstate=None):
 214         if initial_regs is None:
 215             initial_regs = [0] * 32
 216         simulator = run_tst(prog, initial_regs, svstate=svstate)
 217         simulator.gpr.dump()
 218         return simulator
 219
 220
 221 if __name__ == "__main__":
 222     unittest.main()