src/openpower/decoder/isa/test_caller_svp64_bc.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18
  19 class DecoderTestCase(FHDLTestCase):
  20
  21     def _check_regs(self, sim, expected):
  22         for i in range(32):
  23             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  24
  25     def tst_sv_load_store(self):
  26         """>>> lst = ["addi 1, 0, 0x0010",
  27                         "addi 2, 0, 0x0008",
  28                         "addi 5, 0, 0x1234",
  29                         "addi 6, 0, 0x1235",
  30                         "sv.stw *5, 0(*1)",
  31                         "sv.lwz *9, 0(*1)"]
  32         """
  33         lst = SVP64Asm(["addi 1, 0, 0x0010",
  34                         "addi 2, 0, 0x0008",
  35                         "addi 5, 0, 0x1234",
  36                         "addi 6, 0, 0x1235",
  37                         "sv.stw *5, 0(*1)",
  38                         "sv.lwz *9, 0(*1)"])
  39         lst = list(lst)
  40
  41         # SVSTATE (in this case, VL=2)
  42         svstate = SVP64State()
  43         svstate.vl = 2 # VL
  44         svstate.maxvl = 2 # MAXVL
  45         print ("SVSTATE", bin(svstate.asint()))
  46
  47         with Program(lst, bigendian=False) as program:
  48             sim = self.run_tst_program(program, svstate=svstate)
  49             print(sim.gpr(1))
  50             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  51             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  52
  53     def test_sv_branch_cond(self):
  54         for i in [0, 10]: #, 10]: #[0, 10]:
  55             lst = SVP64Asm(
  56                 [f"addi 1, 0, {i}",  # set r1 to i
  57                  f"addi 2, 0, {i}",  # set r2 to i
  58                 "cmpi cr0, 1, 1, 10",  # compare r1 with 10 and store to cr0
  59                 "cmpi cr1, 1, 2, 10",  # compare r2 with 10 and store to cr1
  60                 "sv.bc 12, *2, 0xc",    # beq 0xc -
  61                                        # branch if r1 equals 10 to the nop below
  62                 "addi 3, 0, 0x1234",   # if r1 == 10 this shouldn't execute
  63                 "or 0, 0, 0"]          # branch target
  64                 )
  65             lst = list(lst)
  66
  67             # SVSTATE (in this case, VL=2)
  68             svstate = SVP64State()
  69             svstate.vl = 2 # VL
  70             svstate.maxvl = 2 # MAXVL
  71             print ("SVSTATE", bin(svstate.asint()))
  72
  73             with Program(lst, bigendian=False) as program:
  74                 sim = self.run_tst_program(program, svstate=svstate)
  75                 if i == 10:
  76                     self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
  77                 else:
  78                     self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
  79
  80     def test_sv_branch_cond_all(self):
  81         for i in [7, 8, 9]:
  82             lst = SVP64Asm(
  83                 [f"addi 1, 0, {i+1}",  # set r1 to i
  84                  f"addi 2, 0, {i}",  # set r2 to i
  85                 "cmpi cr0, 1, 1, 8",  # compare r1 with 10 and store to cr0
  86                 "cmpi cr1, 1, 2, 8",  # compare r2 with 10 and store to cr1
  87                 "sv.bc/all 12, *1, 0xc",    # bgt 0xc - branch if BOTH
  88                                        # r1 AND r2 greater 8 to the nop below
  89                 "addi 3, 0, 0x1234",   # if tests fail this shouldn't execute
  90                 "or 0, 0, 0"]          # branch target
  91                 )
  92             lst = list(lst)
  93
  94             # SVSTATE (in this case, VL=2)
  95             svstate = SVP64State()
  96             svstate.vl = 2 # VL
  97             svstate.maxvl = 2 # MAXVL
  98             print ("SVSTATE", bin(svstate.asint()))
  99
 100             with Program(lst, bigendian=False) as program:
 101                 sim = self.run_tst_program(program, svstate=svstate)
 102                 if i == 9:
 103                     self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
 104                 else:
 105                     self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 106
 107     def tst_sv_add_cr(self):
 108         """>>> lst = ['sv.add. *1, *5, *9'
 109                        ]
 110
 111         adds when Rc=1:                               TODO CRs higher up
 112             * 1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 113             * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 114         """
 115         isa = SVP64Asm(['sv.add. *1, *5, *9'
 116                        ])
 117         lst = list(isa)
 118         print ("listing", lst)
 119
 120         # initial values in GPR regfile
 121         initial_regs = [0] * 32
 122         initial_regs[9] = 0xffffffffffffffff
 123         initial_regs[10] = 0x1111
 124         initial_regs[5] = 0x1
 125         initial_regs[6] = 0x2223
 126         # SVSTATE (in this case, VL=2)
 127         svstate = SVP64State()
 128         svstate.vl = 2 # VL
 129         svstate.maxvl = 2 # MAXVL
 130         print ("SVSTATE", bin(svstate.asint()))
 131         # copy before running
 132         expected_regs = deepcopy(initial_regs)
 133         expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x0
 134         expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334
 135
 136         with Program(lst, bigendian=False) as program:
 137             sim = self.run_tst_program(program, initial_regs, svstate)
 138             # XXX TODO, these need to move to higher range (offset)
 139             cr0_idx = SVP64CROffs.CR0
 140             cr1_idx = SVP64CROffs.CR1
 141             CR0 = sim.crl[cr0_idx].get_range().value
 142             CR1 = sim.crl[cr1_idx].get_range().value
 143             print ("CR0", CR0)
 144             print ("CR1", CR1)
 145             self._check_regs(sim, expected_regs)
 146             self.assertEqual(CR0, SelectableInt(2, 4))
 147             self.assertEqual(CR1, SelectableInt(4, 4))
 148
 149     def run_tst_program(self, prog, initial_regs=None,
 150                               svstate=None):
 151         if initial_regs is None:
 152             initial_regs = [0] * 32
 153         simulator = run_tst(prog, initial_regs, svstate=svstate)
 154         simulator.gpr.dump()
 155         return simulator
 156
 157
 158 if __name__ == "__main__":
 159     unittest.main()