src/openpower/decoder/isa/test_caller_svp64_bc.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18
  19 class DecoderTestCase(FHDLTestCase):
  20
  21     def _check_regs(self, sim, expected):
  22         for i in range(32):
  23             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  24
  25     def tst_sv_load_store(self):
  26         """>>> lst = ["addi 1, 0, 0x0010",
  27                         "addi 2, 0, 0x0008",
  28                         "addi 5, 0, 0x1234",
  29                         "addi 6, 0, 0x1235",
  30                         "sv.stw 5.v, 0(1.v)",
  31                         "sv.lwz 9.v, 0(1.v)"]
  32         """
  33         lst = SVP64Asm(["addi 1, 0, 0x0010",
  34                         "addi 2, 0, 0x0008",
  35                         "addi 5, 0, 0x1234",
  36                         "addi 6, 0, 0x1235",
  37                         "sv.stw 5.v, 0(1.v)",
  38                         "sv.lwz 9.v, 0(1.v)"])
  39         lst = list(lst)
  40
  41         # SVSTATE (in this case, VL=2)
  42         svstate = SVP64State()
  43         svstate.vl = 2 # VL
  44         svstate.maxvl = 2 # MAXVL
  45         print ("SVSTATE", bin(svstate.asint()))
  46
  47         with Program(lst, bigendian=False) as program:
  48             sim = self.run_tst_program(program, svstate=svstate)
  49             print(sim.gpr(1))
  50             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  51             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  52
  53     def test_sv_branch_cond(self):
  54         for i in [0]: #[0, 10]:
  55             lst = SVP64Asm(
  56                 [f"addi 1, 0, {i}",  # set r1 to i
  57                 "cmpi cr0, 1, 1, 10",  # compare r1 with 10 and store to cr0
  58                 "sv.bc 12, 2, 0x8",    # beq 0x8 -
  59                                        # branch if r1 equals 10 to the nop below
  60                 "addi 2, 0, 0x1234",   # if r1 == 10 this shouldn't execute
  61                 "or 0, 0, 0"]          # branch target
  62                 )
  63             lst = list(lst)
  64
  65             # SVSTATE (in this case, VL=2)
  66             svstate = SVP64State()
  67             svstate.vl = 2 # VL
  68             svstate.maxvl = 2 # MAXVL
  69             print ("SVSTATE", bin(svstate.asint()))
  70
  71             with Program(lst, bigendian=False) as program:
  72                 sim = self.run_tst_program(program, svstate=svstate)
  73                 if i == 10:
  74                     self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
  75                 else:
  76                     self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
  77
  78     def tst_sv_add_cr(self):
  79         """>>> lst = ['sv.add. 1.v, 5.v, 9.v'
  80                        ]
  81
  82         adds when Rc=1:                               TODO CRs higher up
  83             * 1 = 5 + 9   => 0 = -1+1                 CR0=0b100
  84             * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
  85         """
  86         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
  87                        ])
  88         lst = list(isa)
  89         print ("listing", lst)
  90
  91         # initial values in GPR regfile
  92         initial_regs = [0] * 32
  93         initial_regs[9] = 0xffffffffffffffff
  94         initial_regs[10] = 0x1111
  95         initial_regs[5] = 0x1
  96         initial_regs[6] = 0x2223
  97         # SVSTATE (in this case, VL=2)
  98         svstate = SVP64State()
  99         svstate.vl = 2 # VL
 100         svstate.maxvl = 2 # MAXVL
 101         print ("SVSTATE", bin(svstate.asint()))
 102         # copy before running
 103         expected_regs = deepcopy(initial_regs)
 104         expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x0
 105         expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334
 106
 107         with Program(lst, bigendian=False) as program:
 108             sim = self.run_tst_program(program, initial_regs, svstate)
 109             # XXX TODO, these need to move to higher range (offset)
 110             cr0_idx = SVP64CROffs.CR0
 111             cr1_idx = SVP64CROffs.CR1
 112             CR0 = sim.crl[cr0_idx].get_range().value
 113             CR1 = sim.crl[cr1_idx].get_range().value
 114             print ("CR0", CR0)
 115             print ("CR1", CR1)
 116             self._check_regs(sim, expected_regs)
 117             self.assertEqual(CR0, SelectableInt(2, 4))
 118             self.assertEqual(CR1, SelectableInt(4, 4))
 119
 120     def run_tst_program(self, prog, initial_regs=None,
 121                               svstate=None):
 122         if initial_regs is None:
 123             initial_regs = [0] * 32
 124         simulator = run_tst(prog, initial_regs, svstate=svstate)
 125         simulator.gpr.dump()
 126         return simulator
 127
 128
 129 if __name__ == "__main__":
 130     unittest.main()