src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.decoder.isa.caller import SVP64State
   6 from openpower.decoder.isa.test_caller import run_tst
   7 from openpower.decoder.selectable_int import SelectableInt
   8 from openpower.simulator.program import Program
   9 from openpower.sv.trans.svp64 import SVP64Asm
  10
  11
  12 class DecoderTestCase(FHDLTestCase):
  13
  14     def _check_regs(self, sim, expected):
  15         for i in range(32):
  16             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  17
  18     def test_sv_addi_ffirst_le(self):
  19         lst = SVP64Asm(["sv.subf./ff=le *0,8,*0"
  20                         ])
  21         lst = list(lst)
  22
  23         # SVSTATE
  24         svstate = SVP64State()
  25         svstate.vl = 4  # VL
  26         svstate.maxvl = 4  # MAXVL
  27         print("SVSTATE", bin(svstate.asint()))
  28
  29         gprs = [0] * 64
  30         gprs[8] = 3
  31         vec = [9, 8, 3, 4]
  32
  33         res = []
  34         cr_res = []
  35         # store GPRs
  36         for i, x in enumerate(vec):
  37             gprs[i] = x
  38
  39         with Program(lst, bigendian=False) as program:
  40             sim = self.run_tst_program(program, initial_regs=gprs,
  41                                        svstate=svstate)
  42             for i in range(4):
  43                 val = sim.gpr(i).value
  44                 res.append(val)
  45                 cr_res.append(0)
  46                 print("i", i, val)
  47             # confirm that the results are as expected
  48             expected = deepcopy(vec)
  49             expected_vl = 0
  50             for i in range(4):
  51                 # calculate expected result and expected CR field
  52                 result = vec[i] - gprs[8]
  53                 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
  54                 cr_res[i] = crf
  55                 if result <= 0:
  56                     break
  57                 # VLi=0 - test comes FIRST!
  58                 expected[i] = result
  59                 # only write out if successful
  60                 expected_vl += 1
  61
  62             for i, v in enumerate(cr_res):
  63                 crf = sim.crl[i].get_range().value
  64                 print ("crf", i, res[i], bin(crf), bin(v))
  65                 self.assertEqual(crf, v)
  66
  67             for i, v in enumerate(res):
  68                 self.assertEqual(v, expected[i])
  69
  70             self.assertEqual(sim.svstate.vl, expected_vl)
  71             self.assertEqual(sim.svstate.maxvl, 4)
  72             self.assertEqual(sim.svstate.srcstep, 0)
  73             self.assertEqual(sim.svstate.dststep, 0)
  74
  75     def test_sv_addi_ffirst(self):
  76         lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0"
  77                         ])
  78         lst = list(lst)
  79
  80         # SVSTATE
  81         svstate = SVP64State()
  82         svstate.vl = 4  # VL
  83         svstate.maxvl = 4  # MAXVL
  84         print("SVSTATE", bin(svstate.asint()))
  85
  86         gprs = [0] * 64
  87         gprs[8] = 3
  88         vec = [9, 8, 3, 4]
  89
  90         res = []
  91         cr_res = []
  92         # store GPRs
  93         for i, x in enumerate(vec):
  94             gprs[i] = x
  95
  96         with Program(lst, bigendian=False) as program:
  97             sim = self.run_tst_program(program, initial_regs=gprs,
  98                                        svstate=svstate)
  99             for i in range(4):
 100                 val = sim.gpr(i).value
 101                 res.append(val)
 102                 cr_res.append(0)
 103                 print("i", i, val)
 104             # confirm that the results are as expected
 105             expected = deepcopy(vec)
 106             for i in range(4):
 107                 result = vec[i] - gprs[8]
 108                 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
 109                 cr_res[i] = crf
 110                 if result == 0:
 111                     break
 112                 # VLi=0 - test comes FIRST!
 113                 expected[i] = result
 114             for i, v in enumerate(cr_res):
 115                 crf = sim.crl[i].get_range().value
 116                 print ("crf", i, res[i], bin(crf), bin(v))
 117                 self.assertEqual(crf, v)
 118
 119             for i, v in enumerate(res):
 120                 self.assertEqual(v, expected[i])
 121
 122             self.assertEqual(sim.svstate.vl, 2)
 123             self.assertEqual(sim.svstate.maxvl, 4)
 124             self.assertEqual(sim.svstate.srcstep, 0)
 125             self.assertEqual(sim.svstate.dststep, 0)
 126
 127     def test_sv_addi_ffirst_rc1(self):
 128         lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0"  # RC1 auto-sets EQ (and Rc=1)
 129                         ])
 130         lst = list(lst)
 131
 132         # SVSTATE
 133         svstate = SVP64State()
 134         svstate.vl = 4  # VL
 135         svstate.maxvl = 4  # MAXVL
 136         print("SVSTATE", bin(svstate.asint()))
 137
 138         gprs = [0] * 64
 139         gprs[8] = 3
 140         vec = [9, 8, 3, 4]
 141
 142         res = []
 143         # store GPRs
 144         for i, x in enumerate(vec):
 145             gprs[i] = x
 146
 147         with Program(lst, bigendian=False) as program:
 148             sim = self.run_tst_program(program, initial_regs=gprs,
 149                                        svstate=svstate)
 150             for i in range(4):
 151                 val = sim.gpr(i).value
 152                 res.append(val)
 153                 print("i", i, val)
 154             # confirm that the results are as expected
 155             expected = deepcopy(vec)
 156             for i in range(4):
 157                 result = expected[i] - gprs[8]
 158                 if result == 0:
 159                     break
 160                 # VLi=0 - test comes FIRST!
 161                 expected[i] = result
 162             for i, v in enumerate(res):
 163                 self.assertEqual(v, expected[i])
 164
 165             self.assertEqual(sim.svstate.vl, 2)
 166             self.assertEqual(sim.svstate.maxvl, 4)
 167             self.assertEqual(sim.svstate.srcstep, 0)
 168             self.assertEqual(sim.svstate.dststep, 0)
 169
 170     def test_sv_addi_ffirst_vli(self):
 171         """data-dependent fail-first with VLi=1, the test comes *after* write
 172         """
 173         lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
 174                         ])
 175         lst = list(lst)
 176
 177         # SVSTATE
 178         svstate = SVP64State()
 179         svstate.vl = 4  # VL
 180         svstate.maxvl = 4  # MAXVL
 181         print("SVSTATE", bin(svstate.asint()))
 182
 183         gprs = [0] * 64
 184         gprs[8] = 3
 185         vec = [9, 8, 3, 4]
 186
 187         res = []
 188         # store GPRs
 189         for i, x in enumerate(vec):
 190             gprs[i] = x
 191
 192         with Program(lst, bigendian=False) as program:
 193             sim = self.run_tst_program(program, initial_regs=gprs,
 194                                        svstate=svstate)
 195             for i in range(4):
 196                 val = sim.gpr(i).value
 197                 res.append(val)
 198                 print("i", i, val)
 199             # confirm that the results are as expected
 200             expected = deepcopy(vec)
 201             for i in range(4):
 202                 # VLi=1 - test comes AFTER write!
 203                 expected[i] -= gprs[8]
 204                 if expected[i] == 0:
 205                     break
 206             for i, v in enumerate(res):
 207                 self.assertEqual(v, expected[i])
 208
 209             self.assertEqual(sim.svstate.vl, 3)
 210             self.assertEqual(sim.svstate.maxvl, 4)
 211             self.assertEqual(sim.svstate.srcstep, 0)
 212             self.assertEqual(sim.svstate.dststep, 0)
 213
 214     def run_tst_program(self, prog, initial_regs=None,
 215                         svstate=None,
 216                         initial_mem=None,
 217                         initial_fprs=None):
 218         if initial_regs is None:
 219             initial_regs = [0] * 32
 220         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 221                             initial_fprs=initial_fprs,
 222                             svstate=svstate)
 223
 224         print("GPRs")
 225         simulator.gpr.dump()
 226         print("FPRs")
 227         simulator.fpr.dump()
 228
 229         return simulator
 230
 231
 232 if __name__ == "__main__":
 233     unittest.main()