src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.decoder.isa.caller import SVP64State
   6 from openpower.decoder.isa.test_caller import run_tst
   7 from openpower.decoder.selectable_int import SelectableInt
   8 from openpower.simulator.program import Program
   9 from openpower.sv.trans.svp64 import SVP64Asm
  10
  11
  12 class DecoderTestCase(FHDLTestCase):
  13
  14     def _check_regs(self, sim, expected):
  15         for i in range(32):
  16             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  17
  18     def test_sv_addi_ffirst_le(self):
  19         lst = SVP64Asm(["sv.subf./ff=le *0,8,*0"
  20                         ])
  21         lst = list(lst)
  22
  23         # SVSTATE
  24         svstate = SVP64State()
  25         svstate.vl = 4  # VL
  26         svstate.maxvl = 4  # MAXVL
  27         print("SVSTATE", bin(svstate.asint()))
  28
  29         gprs = [0] * 64
  30         gprs[8] = 3
  31         vec = [9, 8, 3, 4]
  32
  33         res = []
  34         # store GPRs
  35         for i, x in enumerate(vec):
  36             gprs[i] = x
  37
  38         with Program(lst, bigendian=False) as program:
  39             sim = self.run_tst_program(program, initial_regs=gprs,
  40                                        svstate=svstate)
  41             for i in range(4):
  42                 val = sim.gpr(i).value
  43                 res.append(val)
  44                 print("i", i, val)
  45             # confirm that the results are as expected
  46             expected = deepcopy(vec)
  47             expected_vl = 0
  48             for i in range(4):
  49                 result = expected[i] - gprs[8]
  50                 if result <= 0:
  51                     break
  52                 # VLi=0 - test comes FIRST!
  53                 expected[i] = result
  54                 # only write out if successful
  55                 expected_vl += 1
  56             for i, v in enumerate(res):
  57                 self.assertEqual(v, expected[i])
  58
  59             self.assertEqual(sim.svstate.vl, expected_vl)
  60             self.assertEqual(sim.svstate.maxvl, 4)
  61             self.assertEqual(sim.svstate.srcstep, 0)
  62             self.assertEqual(sim.svstate.dststep, 0)
  63
  64     def test_sv_addi_ffirst(self):
  65         lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0"
  66                         ])
  67         lst = list(lst)
  68
  69         # SVSTATE
  70         svstate = SVP64State()
  71         svstate.vl = 4  # VL
  72         svstate.maxvl = 4  # MAXVL
  73         print("SVSTATE", bin(svstate.asint()))
  74
  75         gprs = [0] * 64
  76         gprs[8] = 3
  77         vec = [9, 8, 3, 4]
  78
  79         res = []
  80         # store GPRs
  81         for i, x in enumerate(vec):
  82             gprs[i] = x
  83
  84         with Program(lst, bigendian=False) as program:
  85             sim = self.run_tst_program(program, initial_regs=gprs,
  86                                        svstate=svstate)
  87             for i in range(4):
  88                 val = sim.gpr(i).value
  89                 res.append(val)
  90                 print("i", i, val)
  91             # confirm that the results are as expected
  92             expected = deepcopy(vec)
  93             for i in range(4):
  94                 result = expected[i] - gprs[8]
  95                 if result == 0:
  96                     break
  97                 # VLi=0 - test comes FIRST!
  98                 expected[i] = result
  99             for i, v in enumerate(res):
 100                 self.assertEqual(v, expected[i])
 101
 102             self.assertEqual(sim.svstate.vl, 2)
 103             self.assertEqual(sim.svstate.maxvl, 4)
 104             self.assertEqual(sim.svstate.srcstep, 0)
 105             self.assertEqual(sim.svstate.dststep, 0)
 106
 107     def test_sv_addi_ffirst_rc1(self):
 108         lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0"  # RC1 auto-sets EQ (and Rc=1)
 109                         ])
 110         lst = list(lst)
 111
 112         # SVSTATE
 113         svstate = SVP64State()
 114         svstate.vl = 4  # VL
 115         svstate.maxvl = 4  # MAXVL
 116         print("SVSTATE", bin(svstate.asint()))
 117
 118         gprs = [0] * 64
 119         gprs[8] = 3
 120         vec = [9, 8, 3, 4]
 121
 122         res = []
 123         # store GPRs
 124         for i, x in enumerate(vec):
 125             gprs[i] = x
 126
 127         with Program(lst, bigendian=False) as program:
 128             sim = self.run_tst_program(program, initial_regs=gprs,
 129                                        svstate=svstate)
 130             for i in range(4):
 131                 val = sim.gpr(i).value
 132                 res.append(val)
 133                 print("i", i, val)
 134             # confirm that the results are as expected
 135             expected = deepcopy(vec)
 136             for i in range(4):
 137                 result = expected[i] - gprs[8]
 138                 if result == 0:
 139                     break
 140                 # VLi=0 - test comes FIRST!
 141                 expected[i] = result
 142             for i, v in enumerate(res):
 143                 self.assertEqual(v, expected[i])
 144
 145             self.assertEqual(sim.svstate.vl, 2)
 146             self.assertEqual(sim.svstate.maxvl, 4)
 147             self.assertEqual(sim.svstate.srcstep, 0)
 148             self.assertEqual(sim.svstate.dststep, 0)
 149
 150     def test_sv_addi_ffirst_vli(self):
 151         """data-dependent fail-first with VLi=1, the test comes *after* write
 152         """
 153         lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
 154                         ])
 155         lst = list(lst)
 156
 157         # SVSTATE
 158         svstate = SVP64State()
 159         svstate.vl = 4  # VL
 160         svstate.maxvl = 4  # MAXVL
 161         print("SVSTATE", bin(svstate.asint()))
 162
 163         gprs = [0] * 64
 164         gprs[8] = 3
 165         vec = [9, 8, 3, 4]
 166
 167         res = []
 168         # store GPRs
 169         for i, x in enumerate(vec):
 170             gprs[i] = x
 171
 172         with Program(lst, bigendian=False) as program:
 173             sim = self.run_tst_program(program, initial_regs=gprs,
 174                                        svstate=svstate)
 175             for i in range(4):
 176                 val = sim.gpr(i).value
 177                 res.append(val)
 178                 print("i", i, val)
 179             # confirm that the results are as expected
 180             expected = deepcopy(vec)
 181             for i in range(4):
 182                 # VLi=1 - test comes AFTER write!
 183                 expected[i] -= gprs[8]
 184                 if expected[i] == 0:
 185                     break
 186             for i, v in enumerate(res):
 187                 self.assertEqual(v, expected[i])
 188
 189             self.assertEqual(sim.svstate.vl, 3)
 190             self.assertEqual(sim.svstate.maxvl, 4)
 191             self.assertEqual(sim.svstate.srcstep, 0)
 192             self.assertEqual(sim.svstate.dststep, 0)
 193
 194     def run_tst_program(self, prog, initial_regs=None,
 195                         svstate=None,
 196                         initial_mem=None,
 197                         initial_fprs=None):
 198         if initial_regs is None:
 199             initial_regs = [0] * 32
 200         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 201                             initial_fprs=initial_fprs,
 202                             svstate=svstate)
 203
 204         print("GPRs")
 205         simulator.gpr.dump()
 206         print("FPRs")
 207         simulator.fpr.dump()
 208
 209         return simulator
 210
 211
 212 if __name__ == "__main__":
 213     unittest.main()