src/openpower/decoder/isa/test_caller_svp64_fp.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18
  19 class DecoderTestCase(FHDLTestCase):
  20
  21     def _check_regs(self, sim, expected):
  22         for i in range(32):
  23             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  24
  25     def tst_sv_fpload(self):
  26         """>>> lst = ["sv.lfsx 2.v, 0, 0.v"
  27                         ]
  28         """
  29         lst = SVP64Asm(["sv.lfsx 2.v, 0, 0.v"
  30                         ])
  31         lst = list(lst)
  32
  33         # SVSTATE (in this case, VL=2)
  34         svstate = SVP64State()
  35         svstate.vl[0:7] = 2 # VL
  36         svstate.maxvl[0:7] = 2 # MAXVL
  37         print ("SVSTATE", bin(svstate.spr.asint()))
  38
  39         # memory addresses 0x0000 and 0x0008
  40         initial_mem = {0x0000: (0x42013333, 8), # 32.3
  41                        0x0008: (0xC0200000, 8), # -2.5
  42                         }
  43
  44         # and RB will move on from 0 for first iteration to 1 in 2nd
  45         # therefore we must point GPR(0) at initial mem 0x0000
  46         # and GPR(1) at initial mem 0x0008
  47         initial_regs = [0] * 32
  48         initial_regs[0] = 0x0000 # points at memory address 0x0000 (element 0)
  49         initial_regs[1] = 0x0008 # points at memory address 0x0008 (element 1)
  50
  51         with Program(lst, bigendian=False) as program:
  52             sim = self.run_tst_program(program, initial_regs,
  53                                                 svstate=svstate,
  54                                                 initial_mem=initial_mem)
  55             print(sim.fpr(2))
  56             print(sim.fpr(3))
  57             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
  58             self.assertEqual(sim.fpr(3), SelectableInt(0xC004000000000000, 64))
  59
  60     def test_fp_single_ldst(self):
  61         """>>> lst = ["sv.lfsx 0.v, 0, 2.v",   # load fp 1/2 from mem 0/8
  62                       "sv.stfsu 0.v, 16(4.v)", # store fp 1/2, update RA *twice*
  63                       "sv.lfs 3.v, 0(4.v)",   # re-load from UPDATED r4/r5
  64                      ]
  65         """
  66         lst = SVP64Asm(["sv.lfsx 0.v, 0, 4.v",
  67                         "sv.stfsu 0.v, 16(4.v)",
  68                         "sv.lfs 3.v, 0(4.v)",
  69                      ])
  70         lst = list(lst)
  71
  72         # SVSTATE (in this case, VL=2)
  73         svstate = SVP64State()
  74         svstate.vl[0:7] = 2 # VL
  75         svstate.maxvl[0:7] = 2 # MAXVL
  76         print ("SVSTATE", bin(svstate.spr.asint()))
  77
  78         # memory addresses 0x0000 and 0x0008
  79         initial_mem = {0x0000: (0x42013333, 8), # 32.3
  80                        0x0008: (0xC0200000, 8), # -2.5
  81                        0x0020: (0x1828384822324252, 8),
  82                         }
  83
  84         # and RB will move on from 0 for first iteration to 1 in 2nd
  85         # therefore we must point GPR(4) at initial mem 0x0000
  86         # and GPR(5) at initial mem 0x0008
  87         initial_regs = [0] * 32
  88         initial_regs[4] = 0x0000 # points at memory address 0x0000 (element 0)
  89         initial_regs[5] = 0x0008 # points at memory address 0x0008 (element 1)
  90
  91         with Program(lst, bigendian=False) as program:
  92             sim = self.run_tst_program(program, initial_regs,
  93                                                 svstate=svstate,
  94                                                 initial_mem=initial_mem)
  95             print("FPR 1", sim.fpr(0))
  96             print("FPR 2", sim.fpr(1))
  97             print("GPR 1", sim.gpr(4)) # should be 0x10 due to update
  98             print("GPR 2", sim.gpr(5)) # should be 0x18 due to update
  99             self.assertEqual(sim.gpr(4), SelectableInt(0x10, 64))
 100             self.assertEqual(sim.gpr(5), SelectableInt(0x18, 64))
 101             self.assertEqual(sim.fpr(0), SelectableInt(0x4040266660000000, 64))
 102             self.assertEqual(sim.fpr(1), SelectableInt(0xC004000000000000, 64))
 103             self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
 104             self.assertEqual(sim.fpr(4), SelectableInt(0xC004000000000000, 64))
 105
 106
 107     def tst_sv_fpadd(self):
 108         """>>> lst = ["sv.fadds 6.v, 2.v, 4.v"
 109                         ]
 110         """
 111         lst = SVP64Asm(["sv.fadds 6.v, 2.v, 4.v"
 112                         ])
 113         lst = list(lst)
 114
 115         fprs = [0] * 32
 116         fprs[2] = 0xC040266660000000 # -32.3
 117         fprs[3] = 0xC040266660000000 # -32.3
 118         fprs[4] = 0x4040266660000000 # +32.3
 119         fprs[5] = 0xC040266660000000 # -32.3
 120
 121         # SVSTATE (in this case, VL=2)
 122         svstate = SVP64State()
 123         svstate.vl[0:7] = 2 # VL
 124         svstate.maxvl[0:7] = 2 # MAXVL
 125         print ("SVSTATE", bin(svstate.spr.asint()))
 126
 127         with Program(lst, bigendian=False) as program:
 128             sim = self.run_tst_program(program, svstate=svstate,
 129                                        initial_fprs=fprs)
 130             self.assertEqual(sim.fpr(6), SelectableInt(0x0, 64))
 131             self.assertEqual(sim.fpr(7), SelectableInt(0xc050266660000000, 64))
 132
 133     def run_tst_program(self, prog, initial_regs=None,
 134                               svstate=None,
 135                               initial_mem=None,
 136                               initial_fprs=None):
 137         if initial_regs is None:
 138             initial_regs = [0] * 32
 139         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 140                                                 initial_fprs=initial_fprs,
 141                                                 svstate=svstate)
 142
 143         print ("GPRs")
 144         simulator.gpr.dump()
 145         print ("FPRs")
 146         simulator.fpr.dump()
 147
 148         return simulator
 149
 150
 151 if __name__ == "__main__":
 152     unittest.main()