src/openpower/decoder/isa/test_caller_svp64_inssort.py

   1 import unittest
   2
   3 from nmutil.formaltest import FHDLTestCase
   4 from openpower.decoder.isa.caller import SVP64State
   5 from openpower.decoder.isa.test_caller import run_tst
   6 from openpower.decoder.selectable_int import SelectableInt
   7 from openpower.simulator.program import Program
   8 from openpower.sv.trans.svp64 import SVP64Asm
   9
  10
  11 def signcopy(x, y):
  12     y = abs(y)
  13     if x < 0:
  14         return -y
  15     return y
  16
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_sv_cmp_ff_vli(self):
  25         lst = SVP64Asm(["sv.cmp/ff=eq/vli *0, 1, *16, 0",
  26                         ])
  27         lst = list(lst)
  28
  29         # SVSTATE vl=10
  30         svstate = SVP64State()
  31         svstate.vl = 3  # VL
  32         svstate.maxvl = 3  # MAXVL
  33         print("SVSTATE", bin(svstate.asint()))
  34
  35         gprs = [0] * 64
  36         vec = [1, 2, 3]
  37         crs_expected = [8, 2, 0]  # LT EQ GT
  38
  39         res = []
  40         # store GPRs
  41         for i, x in enumerate(vec):
  42             gprs[i+16] = x
  43
  44         gprs[0] = 2  # middle value of vec
  45
  46         with Program(lst, bigendian=False) as program:
  47             sim = self.run_tst_program(program, initial_regs=gprs,
  48                                        svstate=svstate)
  49             print("spr svstate ", sim.svstate)
  50             print("          vl", sim.svstate.vl)
  51             for i in range(len(vec)):
  52                 val = sim.gpr(16+i).value
  53                 res.append(val)
  54                 crf = sim.crl[i].get_range().value
  55                 print("i", i, val, crf)
  56             for i in range(len(vec)):
  57                 crf = sim.crl[i].get_range().value
  58                 assert crf == crs_expected[i], "cr %d %s expect %s" % \
  59                     (i, crf, crs_expected[i])
  60             assert sim.svstate.vl == 2
  61
  62     def test_sv_cmp_ff(self):
  63         lst = SVP64Asm(["sv.cmp/ff=eq *0, 1, *16, 0",
  64                         ])
  65         lst = list(lst)
  66
  67         # SVSTATE vl=10
  68         svstate = SVP64State()
  69         svstate.vl = 3  # VL
  70         svstate.maxvl = 3  # MAXVL
  71         print("SVSTATE", bin(svstate.asint()))
  72
  73         gprs = [0] * 64
  74         vec = [1, 2, 3]
  75         crs_expected = [8, 2, 0]  # LT EQ GT
  76
  77         res = []
  78         # store GPRs
  79         for i, x in enumerate(vec):
  80             gprs[i+16] = x
  81
  82         gprs[0] = 2  # middle value of vec
  83
  84         with Program(lst, bigendian=False) as program:
  85             sim = self.run_tst_program(program, initial_regs=gprs,
  86                                        svstate=svstate)
  87             print("spr svstate ", sim.svstate)
  88             print("          vl", sim.svstate.vl)
  89             for i in range(len(vec)):
  90                 val = sim.gpr(16+i).value
  91                 res.append(val)
  92                 crf = sim.crl[i].get_range().value
  93                 print("i", i, val, crf)
  94             for i in range(len(vec)):
  95                 crf = sim.crl[i].get_range().value
  96                 assert crf == crs_expected[i], "cr %d %s expect %s" % \
  97                     (i, crf, crs_expected[i])
  98             assert sim.svstate.vl == 1
  99
 100     def test_sv_cmp_ff_lt(self):
 101         lst = SVP64Asm(["sv.cmp/ff=gt *0, 1, *16, 0",
 102                         ])
 103         lst = list(lst)
 104
 105         # SVSTATE vl=10
 106         svstate = SVP64State()
 107         svstate.vl = 3  # VL
 108         svstate.maxvl = 3  # MAXVL
 109         print("SVSTATE", bin(svstate.asint()))
 110
 111         gprs = [0] * 64
 112         vec = [1, 2, 3]
 113         crs_expected = [8, 2, 4]  # LT EQ GT
 114
 115         res = []
 116         # store GPRs
 117         for i, x in enumerate(vec):
 118             gprs[i+16] = x
 119
 120         gprs[0] = 2  # middle value of vec
 121
 122         with Program(lst, bigendian=False) as program:
 123             sim = self.run_tst_program(program, initial_regs=gprs,
 124                                        svstate=svstate)
 125             print("spr svstate ", sim.svstate)
 126             print("          vl", sim.svstate.vl)
 127             for i in range(len(vec)):
 128                 val = sim.gpr(16+i).value
 129                 res.append(val)
 130                 crf = sim.crl[i].get_range().value
 131                 print("i", i, val, crf)
 132             for i in range(len(vec)):
 133                 crf = sim.crl[i].get_range().value
 134                 assert crf == crs_expected[i], "cr %d %s expect %s" % \
 135                     (i, crf, crs_expected[i])
 136             assert sim.svstate.vl == 2
 137
 138     def test_sv_cmp(self):
 139         lst = SVP64Asm(["sv.cmp *0, 1, *16, 0",
 140                         ])
 141         lst = list(lst)
 142
 143         # SVSTATE vl=10
 144         svstate = SVP64State()
 145         svstate.vl = 3  # VL
 146         svstate.maxvl = 3  # MAXVL
 147         print("SVSTATE", bin(svstate.asint()))
 148
 149         gprs = [0] * 64
 150         vec = [1, 2, 3]
 151         crs_expected = [8, 2, 4]  # LT EQ GT
 152
 153         res = []
 154         # store GPRs
 155         for i, x in enumerate(vec):
 156             gprs[i+16] = x
 157
 158         gprs[0] = 2  # middle value of vec
 159
 160         with Program(lst, bigendian=False) as program:
 161             sim = self.run_tst_program(program, initial_regs=gprs,
 162                                        svstate=svstate)
 163             print("spr svstate ", sim.spr['SVSTATE'])
 164             for i in range(len(vec)):
 165                 val = sim.gpr(16+i).value
 166                 res.append(val)
 167                 crf = sim.crl[i].get_range().value
 168                 print("i", i, val, crf)
 169                 assert crf == crs_expected[i]
 170
 171     def test_sv_insert_sort(self):
 172         """
 173                 ctr = alen-1
 174                 li r10, 1 # prepare mask
 175                 sld r10, alen, r10
 176                 addi r10, r10, -1 # all 1s. must be better way
 177             loop:
 178                 setvl r3, ctr
 179                 sv.mv/m=1<<r3 key, *array   # get key item
 180                 sld r10, 1  # shift in another zero MSB
 181                 sv.cmp/ff=GT/m=~r10 *0, *array, key # stop cmp at 1st GT fail
 182                 sv.mv/m=GT *array-1, *array    # after cmp and ffirst
 183                 getvl r3
 184                 sub r3, 1                   # reduce by one
 185                 sv.mv/m=1<<r3 *array, key   # put key into array
 186                 bc 16, loop                 # dec CTR, back around
 187
 188             def insertion_sort(array):
 189                 lim = len(array)-1
 190                 for i in range(lim,-1,-1):
 191                     key_item = array[i]
 192                     j = i + 1
 193                     while j <= lim and array[j] > key_item:
 194                         array[j - 1] = array[j]
 195                         j += 1
 196                     array[j - 1] = key_item
 197                 return array
 198         """
 199         lst = SVP64Asm(["addi 10, 0, 1",
 200                         "addi 9, 11, 0",
 201                         "slw 10, 10, 9",
 202                         "addi 10, 10, -1",
 203                         "mtspr 9, 11",
 204                         "setvl 3, 0, 10, 0, 1, 1",
 205                         "addi 3, 3, -1",
 206                         "sv.addi/m=1<<r3 12, *16, 0",  # key item to 12
 207                         "sv.cmp/ff=lt/m=~r10 *0, 1, *16, 12",
 208                         "sv.addi/m=ge *16, *17, 0",  # move down
 209                         "setvl 3, 0, 0, 0, 0, 0",  # get VL into r3
 210                         "addi 3, 3, -1",
 211                         "setvl 13, 0, 10, 0, 1, 1",  # put VL back from CTR
 212                         "sv.addi/m=1<<r3 *16, 12, 0",  # restore key
 213                         "slw 10, 10, 9",  # shift up start-mask ("inc" j)
 214                         "bc 16, 0, -52",  # decrement CTR, repeat
 215                         ])
 216         lst = list(lst)
 217
 218         gprs = [0] * 64
 219         #vec = [1, 2, 3, 4, 9, 5, 6]
 220         vec = [9, 5, 6]
 221
 222         res = []
 223         # store GPRs
 224         for i, x in enumerate(vec):
 225             gprs[i+16] = x
 226
 227         gprs[11] = len(vec)
 228
 229         with Program(lst, bigendian=False) as program:
 230             sim = self.run_tst_program(program, initial_regs=gprs)
 231             print("spr svstate ", sim.spr['SVSTATE'])
 232             print("spr svshape0", sim.spr['SVSHAPE0'])
 233             print("    xdimsz", sim.spr['SVSHAPE0'].xdimsz)
 234             print("    ydimsz", sim.spr['SVSHAPE0'].ydimsz)
 235             print("    zdimsz", sim.spr['SVSHAPE0'].zdimsz)
 236             print("spr svshape1", sim.spr['SVSHAPE1'])
 237             print("spr svshape2", sim.spr['SVSHAPE2'])
 238             print("spr svshape3", sim.spr['SVSHAPE3'])
 239             for i in range(len(vec)):
 240                 val = sim.gpr(16+i).value
 241                 res.append(val)
 242                 crf = sim.crl[i].get_range().value
 243                 print("i", i, val, crf)
 244             return
 245             # confirm that the results are as expected
 246             expected = list(reversed(sorted(vec)))
 247             for i, v in enumerate(res):
 248                 self.assertEqual(v, expected[i])
 249
 250     def run_tst_program(self, prog, initial_regs=None,
 251                         svstate=None,
 252                         initial_mem=None,
 253                         initial_fprs=None):
 254         if initial_regs is None:
 255             initial_regs = [0] * 32
 256         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 257                             initial_fprs=initial_fprs,
 258                             svstate=svstate)
 259
 260         print("GPRs")
 261         simulator.gpr.dump()
 262         print("FPRs")
 263         simulator.fpr.dump()
 264
 265         return simulator
 266
 267
 268 if __name__ == "__main__":
 269     unittest.main()