src/openpower/decoder/isa/test_caller_svp64_ldst.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from openpower.decoder.helpers import fp64toselectable
  17 from openpower.decoder.isa.remap_dct_yield import (halfrev2, reverse_bits,
  18                                                   )
  19 from copy import deepcopy
  20
  21
  22 class DecoderTestCase(FHDLTestCase):
  23
  24     def _check_regs(self, sim, expected):
  25         for i in range(32):
  26             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  27
  28     def _check_fpregs(self, sim, expected):
  29         for i in range(32):
  30             self.assertEqual(sim.fpr(i), SelectableInt(expected[i], 64))
  31
  32     def test_sv_load_store_elementstride(self):
  33         """>>> lst = ["addi 2, 0, 0x0010",
  34                         "addi 3, 0, 0x0008",
  35                         "addi 4, 0, 0x1234",
  36                         "addi 5, 0, 0x1235",
  37                         "sv.stw/els *4, 16(2)",
  38                         "sv.lwz/els *8, 16(2)"]
  39
  40         note: element stride mode is only enabled when RA is a scalar
  41         and when the immediate is non-zero
  42
  43         element stride is computed as:
  44         for i in range(VL):
  45             EA = (RA|0) + EXTS(D) * i
  46         """
  47         lst = SVP64Asm(["addi 2, 0, 0x0010",
  48                         "addi 3, 0, 0x0008",
  49                         "addi 4, 0, 0x1234",
  50                         "addi 5, 0, 0x1235",
  51                         "sv.stw/els *4, 24(2)",  # scalar r1 + 16 + 24*offs
  52                         "sv.lwz/els *8, 24(2)"]) # scalar r1 + 16 + 24*offs
  53         lst = list(lst)
  54
  55         # SVSTATE (in this case, VL=2)
  56         svstate = SVP64State()
  57         svstate.vl = 2 # VL
  58         svstate.maxvl = 2 # MAXVL
  59         print ("SVSTATE", bin(svstate.asint()))
  60
  61         with Program(lst, bigendian=False) as program:
  62             sim = self.run_tst_program(program, svstate=svstate)
  63             mem = sim.mem.dump(printout=False)
  64             print (mem)
  65             # contents of memory expected at:
  66             #    element 0:   r1=0x10, D=24, => EA = 0x10+24*0 = 16 (0x10)
  67             #    element 1:   r1=0x10, D=24, => EA = 0x10+24*1 = 40 (0x28)
  68             # therefore, at address 0x10 ==> 0x1234
  69             # therefore, at address 0x28 ==> 0x1235
  70             expected_mem = [(16, 0x1234),
  71                             (40, 0x1235)]
  72             self.assertEqual(mem, expected_mem)
  73             print(sim.gpr(1))
  74             self.assertEqual(sim.gpr(8), SelectableInt(0x1234, 64))
  75             self.assertEqual(sim.gpr(9), SelectableInt(0x1235, 64))
  76
  77     def test_sv_load_store_unitstride(self):
  78         """>>> lst = ["addi 1, 0, 0x0010",
  79                         "addi 2, 0, 0x0008",
  80                         "addi 5, 0, 0x1234",
  81                         "addi 6, 0, 0x1235",
  82                         "sv.stw *8, 8(1)",
  83                         "sv.lwz *12, 8(1)"]
  84
  85         note: unit stride mode is only enabled when RA is a scalar.
  86
  87         unit stride is computed as:
  88         for i in range(VL):
  89             EA = (RA|0) + EXTS(D) + LDSTsize * i
  90         where for stw and lwz, LDSTsize is 4 because it is 32-bit words
  91         """
  92         lst = SVP64Asm(["addi 1, 0, 0x0010",
  93                         "addi 2, 0, 0x0008",
  94                         "addi 8, 0, 0x1234",
  95                         "addi 9, 0, 0x1235",
  96                         "sv.stw *8, 8(1)",  # scalar r1 + 8 + wordlen*offs
  97                         "sv.lwz *12, 8(1)"]) # scalar r1 + 8 + wordlen*offs
  98         lst = list(lst)
  99
 100         # SVSTATE (in this case, VL=2)
 101         svstate = SVP64State()
 102         svstate.vl = 2 # VL
 103         svstate.maxvl = 2 # MAXVL
 104         print ("SVSTATE", bin(svstate.asint()))
 105
 106         with Program(lst, bigendian=False) as program:
 107             sim = self.run_tst_program(program, svstate=svstate)
 108             mem = sim.mem.dump(printout=False)
 109             print ("Mem")
 110             print (mem)
 111             # contents of memory expected at:
 112             #    element 0:   r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*0 = 0x24
 113             #    element 1:   r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*8 = 0x28
 114             # therefore, at address 0x24 ==> 0x1234
 115             # therefore, at address 0x28 ==> 0x1235
 116             self.assertEqual(mem, [(24, 0x123500001234)])
 117             print(sim.gpr(1))
 118             self.assertEqual(sim.gpr(12), SelectableInt(0x1234, 64))
 119             self.assertEqual(sim.gpr(13), SelectableInt(0x1235, 64))
 120
 121     @unittest.skip("deprecated, needs Scalar LDST-shifted")
 122     def test_sv_load_store_shifted(self):
 123         """>>> lst = ["addi 1, 0, 0x0010",
 124                         "addi 2, 0, 0x0004",
 125                         "addi 3, 0, 0x0002",
 126                         "addi 4, 0, 0x101",
 127                         "addi 5, 0, 0x202",
 128                         "addi 6, 0, 0x303",
 129                         "addi 7, 0, 0x404",
 130                         "sv.stw *4, 0(1)",
 131                         "sv.lwzsh *12, 4(1), 2"]
 132
 133         shifted LD is computed as:
 134         for i in range(VL):
 135             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 136         """
 137         lst = SVP64Asm(["addi 1, 0, 0x0010",
 138                         "addi 2, 0, 0x0000",
 139                         "addi 4, 0, 0x101",
 140                         "addi 5, 0, 0x202",
 141                         "addi 6, 0, 0x303",
 142                         "addi 7, 0, 0x404",
 143                         "sv.stw *4, 0(1)",  # scalar r1 + 0 + wordlen*offs
 144                         "sv.lwzsh *12, 4(1), 2"]) # bit-reversed
 145         lst = list(lst)
 146
 147         # SVSTATE (in this case, VL=4)
 148         svstate = SVP64State()
 149         svstate.vl = 4 # VL
 150         svstate.maxvl = 4 # MAXVL
 151         print ("SVSTATE", bin(svstate.asint()))
 152
 153         with Program(lst, bigendian=False) as program:
 154             sim = self.run_tst_program(program, svstate=svstate)
 155             mem = sim.mem.dump(printout=False)
 156             print (mem)
 157
 158             self.assertEqual(mem, [(16, 0x020200000101),
 159                                    (24, 0x040400000303)])
 160             print(sim.gpr(1))
 161             # from STs
 162             self.assertEqual(sim.gpr(4), SelectableInt(0x101, 64))
 163             self.assertEqual(sim.gpr(5), SelectableInt(0x202, 64))
 164             self.assertEqual(sim.gpr(6), SelectableInt(0x303, 64))
 165             self.assertEqual(sim.gpr(7), SelectableInt(0x404, 64))
 166             # r1=0x10, RC=0, offs=4: contents of memory expected at:
 167             #    element 0:   EA = r1 + 0b00*4 => 0x10 + 0b00*4 => 0x10
 168             #    element 1:   EA = r1 + 0b01*4 => 0x10 + 0b01*4 => 0x18
 169             #    element 2:   EA = r1 + 0b10*4 => 0x10 + 0b10*4 => 0x14
 170             #    element 3:   EA = r1 + 0b11*4 => 0x10 + 0b11*4 => 0x1c
 171             # therefore loaded from (bit-reversed indexing):
 172             #    r9  => mem[0x10] which was stored from r5
 173             #    r10 => mem[0x18] which was stored from r6
 174             #    r11 => mem[0x18] which was stored from r7
 175             #    r12 => mem[0x1c] which was stored from r8
 176             self.assertEqual(sim.gpr(12), SelectableInt(0x101, 64))
 177             self.assertEqual(sim.gpr(13), SelectableInt(0x202, 64))
 178             self.assertEqual(sim.gpr(14), SelectableInt(0x303, 64))
 179             self.assertEqual(sim.gpr(15), SelectableInt(0x404, 64))
 180
 181     @unittest.skip("deprecated, needs Scalar LDST-shifted")
 182     def test_sv_load_store_shifted_fp(self):
 183         """>>> lst = ["addi 1, 0, 0x0010",
 184                         "addi 2, 0, 0x0004",
 185                         "addi 3, 0, 0x0002",
 186                         "addi 4, 0, 0x101",
 187                         "addi 5, 0, 0x202",
 188                         "addi 6, 0, 0x303",
 189                         "addi 7, 0, 0x404",
 190                         "sv.std *4, 0(1)",
 191                         "sv.lfdbr *12, 4(1), 2"]
 192
 193         shifted LD is computed as:
 194         for i in range(VL):
 195             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 196         """
 197         lst = SVP64Asm(["addi 1, 0, 0x0010",
 198                         "addi 2, 0, 0x0000",
 199                         "addi 4, 0, 0x101",
 200                         "addi 5, 0, 0x202",
 201                         "addi 6, 0, 0x303",
 202                         "addi 7, 0, 0x404",
 203                         "sv.std *4, 0(1)", # scalar r1 + 0 + wordlen*offs
 204                         "sv.lfdsh *12, 8(1), 2"]) # shifted
 205         lst = list(lst)
 206
 207         # SVSTATE (in this case, VL=4)
 208         svstate = SVP64State()
 209         svstate.vl = 4 # VL
 210         svstate.maxvl = 4 # MAXVL
 211         print ("SVSTATE", bin(svstate.asint()))
 212
 213         fprs = [0] * 32
 214
 215         with Program(lst, bigendian=False) as program:
 216             sim = self.run_tst_program(program, svstate=svstate,
 217                                                 initial_fprs=fprs)
 218             mem = sim.mem.dump(printout=False)
 219             print (mem)
 220
 221             self.assertEqual(mem, [(16, 0x101),
 222                                    (24, 0x202),
 223                                    (32, 0x303),
 224                                    (40, 0x404),
 225                                   ])
 226             print(sim.gpr(1))
 227             # from STs
 228             self.assertEqual(sim.gpr(4), SelectableInt(0x101, 64))
 229             self.assertEqual(sim.gpr(5), SelectableInt(0x202, 64))
 230             self.assertEqual(sim.gpr(6), SelectableInt(0x303, 64))
 231             self.assertEqual(sim.gpr(7), SelectableInt(0x404, 64))
 232             # r1=0x10, RC=0, offs=4: contents of memory expected at:
 233             #    element 0:   EA = r1 + bitrev(0b00)*4 => 0x10 + 0b00*4 => 0x10
 234             #    element 1:   EA = r1 + bitrev(0b01)*4 => 0x10 + 0b10*4 => 0x18
 235             #    element 2:   EA = r1 + bitrev(0b10)*4 => 0x10 + 0b01*4 => 0x14
 236             #    element 3:   EA = r1 + bitrev(0b11)*4 => 0x10 + 0b10*4 => 0x1c
 237             # therefore loaded from (bit-reversed indexing):
 238             #    r9  => mem[0x10] which was stored from r5
 239             #    r10 => mem[0x18] which was stored from r6
 240             #    r11 => mem[0x18] which was stored from r7
 241             #    r12 => mem[0x1c] which was stored from r8
 242             self.assertEqual(sim.fpr(12), SelectableInt(0x101, 64))
 243             self.assertEqual(sim.fpr(13), SelectableInt(0x202, 64))
 244             self.assertEqual(sim.fpr(14), SelectableInt(0x303, 64))
 245             self.assertEqual(sim.fpr(15), SelectableInt(0x404, 64))
 246
 247     @unittest.skip("deprecated, needs Scalar LDST-shifted")
 248     def test_sv_load_store_shifted2(self):
 249         """>>> lst = ["addi 1, 0, 0x0010",
 250                         "addi 2, 0, 0x0004",
 251                         "addi 3, 0, 0x0002",
 252                         "sv.stfs *4, 0(1)",
 253                         "sv.lfssh *12, 4(1), 2"]
 254
 255         shifted LD is computed as:
 256         for i in range(VL):
 257             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 258
 259         """
 260         lst = SVP64Asm(["addi 1, 0, 0x0010",
 261                         "addi 2, 0, 0x0000",
 262                         "sv.stfs *4, 0(1)",  # scalar r1 + 0 + wordlen*offs
 263                         "sv.lfssh *12, 4(1), 2"]) # shifted (by zero, but hey)
 264         lst = list(lst)
 265
 266         # SVSTATE (in this case, VL=4)
 267         svstate = SVP64State()
 268         svstate.vl = 4 # VL
 269         svstate.maxvl = 4 # MAXVL
 270         print ("SVSTATE", bin(svstate.asint()))
 271
 272         fprs = [0] * 32
 273         scalar_a = 1.3
 274         scalar_b = -2.0
 275         fprs[4] = fp64toselectable(1.0)
 276         fprs[5] = fp64toselectable(2.0)
 277         fprs[6] = fp64toselectable(3.0)
 278         fprs[7] = fp64toselectable(4.0)
 279
 280         # expected results, remember that bit-reversed load has been done
 281         expected_fprs = deepcopy(fprs)
 282         expected_fprs[12] = fprs[4] # 0b00 -> 0b00
 283         expected_fprs[13] = fprs[5] # 0b10 -> 0b01
 284         expected_fprs[14] = fprs[6] # 0b01 -> 0b10
 285         expected_fprs[15] = fprs[7] # 0b11 -> 0b11
 286
 287         with Program(lst, bigendian=False) as program:
 288             sim = self.run_tst_program(program, svstate=svstate,
 289                                                 initial_fprs=fprs)
 290             mem = sim.mem.dump(printout=False)
 291             print ("mem dump")
 292             print (mem)
 293
 294             print ("FPRs")
 295             sim.fpr.dump()
 296
 297             #self.assertEqual(mem, [(16, 0x020200000101),
 298             #                       (24, 0x040400000303)])
 299             self._check_fpregs(sim, expected_fprs)
 300
 301     def test_sv_load_store_remap_matrix(self):
 302         """>>> lst = ["addi 1, 0, 0x0010",
 303                         "addi 2, 0, 0x0004",
 304                         "addi 3, 0, 0x0002",
 305                         "addi 5, 0, 0x101",
 306                         "addi 6, 0, 0x202",
 307                         "addi 7, 0, 0x303",
 308                         "addi 8, 0, 0x404",
 309                         "sv.stw *4, 0(1)",  # scalar r1 + 0 + wordlen*offs
 310                         "svshape 3, 3, 4, 0, 0",
 311                         "svremap 1, 1, 2, 0, 0, 0, 0",
 312                         "sv.lwz *20, 0(1)",
 313                         ]
 314
 315         REMAPed a LD operation via a Matrix Multiply Schedule,
 316         which is set up as 3x4 result
 317         """
 318         lst = SVP64Asm(["addi 1, 0, 0x0010",
 319                         "addi 2, 0, 0x0000",
 320                         "addi 4, 0, 0x101",
 321                         "addi 5, 0, 0x202",
 322                         "addi 6, 0, 0x303",
 323                         "addi 7, 0, 0x404",
 324                         "addi 8, 0, 0x505",
 325                         "addi 9, 0, 0x606",
 326                         "addi 10, 0, 0x707",
 327                         "addi 11, 0, 0x808",
 328                         "addi 12, 0, 0x909",
 329                         "addi 13, 0, 0xa0a",
 330                         "addi 14, 0, 0xb0b",
 331                         "addi 15, 0, 0xc0c",
 332                         "addi 16, 0, 0xd0d",
 333                         "addi 17, 0, 0xe0e",
 334                         "addi 18, 0, 0xf0f",
 335                         "sv.stw *4, 0(1)",  # scalar r1 + 0 + wordlen*offs
 336                         "svshape 3, 3, 4, 0, 0",
 337                         "svremap 1, 1, 2, 0, 0, 0, 0",
 338                         "sv.lwz *20, 0(1)",
 339                         ])
 340         lst = list(lst)
 341
 342         # SVSTATE (in this case, VL=4)
 343         svstate = SVP64State()
 344         svstate.vl = 12 # VL
 345         svstate.maxvl = 12 # MAXVL
 346         print ("SVSTATE", bin(svstate.asint()))
 347
 348         regs = [0] * 64
 349
 350         with Program(lst, bigendian=False) as program:
 351             sim = self.run_tst_program(program, svstate=svstate,
 352                                                 initial_regs=regs)
 353             mem = sim.mem.dump(printout=False)
 354             print ("Mem")
 355             print (mem)
 356
 357             self.assertEqual(mem, [(16, 0x020200000101),
 358                                    (24, 0x040400000303),
 359                                    (32, 0x060600000505),
 360                                    (40, 0x080800000707),
 361                                    (48, 0x0a0a00000909),
 362                                    (56, 0x0c0c00000b0b)])
 363             print(sim.gpr(1))
 364             # from STs
 365             self.assertEqual(sim.gpr(4), SelectableInt(0x101, 64))
 366             self.assertEqual(sim.gpr(5), SelectableInt(0x202, 64))
 367             self.assertEqual(sim.gpr(6), SelectableInt(0x303, 64))
 368             self.assertEqual(sim.gpr(7), SelectableInt(0x404, 64))
 369             self.assertEqual(sim.gpr(8), SelectableInt(0x505, 64))
 370             self.assertEqual(sim.gpr(9), SelectableInt(0x606, 64))
 371             self.assertEqual(sim.gpr(10), SelectableInt(0x707, 64))
 372             self.assertEqual(sim.gpr(11), SelectableInt(0x808, 64))
 373             # combination of bit-reversed load with a Matrix REMAP
 374             # schedule
 375             for i in range(3):
 376                 self.assertEqual(sim.gpr(20+i), SelectableInt(0x101, 64))
 377                 self.assertEqual(sim.gpr(23+i), SelectableInt(0x505, 64))
 378                 self.assertEqual(sim.gpr(26+i), SelectableInt(0x909, 64))
 379                 self.assertEqual(sim.gpr(29+i), SelectableInt(0x202, 64))
 380
 381     def test_sv_load_store_bitreverse_remap_halfswap(self):
 382         """>>> lst = ["addi 1, 0, 0x0010",
 383                         "addi 2, 0, 0x0000",
 384                         "addi 4, 0, 0x101",
 385                         "addi 5, 0, 0x202",
 386                         "addi 6, 0, 0x303",
 387                         "addi 7, 0, 0x404",
 388                         "addi 8, 0, 0x505",
 389                         "addi 9, 0, 0x606",
 390                         "addi 10, 0, 0x707",
 391                         "addi 11, 0, 0x808",
 392                         "sv.stw *5, 0(1)",
 393                         "svshape 8, 1, 1, 6, 0",
 394                         "svremap 31, 1, 2, 3, 0, 0, 0",
 395                         "sv.lwz/els *12, 4(1)"]
 396
 397         shifted LD is computed as:
 398         for i in range(VL):
 399             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 400
 401         bitreversal of 0 1 2 3 in binary 0b00 0b01 0b10 0b11
 402         produces       0 2 1 3 in binary 0b00 0b10 0b01 0b11
 403
 404         and thus creates the butterfly needed for one iteration of FFT.
 405         the RC (shift) is to be able to offset the LDs by Radix-2 spans
 406
 407         on top of the bit-reversal is a REMAP for half-swaps for DCT
 408         in-place.
 409         """
 410         lst = SVP64Asm(["addi 1, 0, 0x0010",
 411                         "addi 2, 0, 0x0000",
 412                         "addi 4, 0, 0x001",
 413                         "addi 5, 0, 0x102",
 414                         "addi 6, 0, 0x203",
 415                         "addi 7, 0, 0x304",
 416                         "addi 8, 0, 0x405",
 417                         "addi 9, 0, 0x506",
 418                         "addi 10, 0, 0x607",
 419                         "addi 11, 0, 0x708",
 420                         "sv.stw *4, 0(1)",  # scalar r1 + 0 + wordlen*offs
 421                         "svshape 8, 1, 1, 6, 0",
 422                         "svremap 1, 0, 0, 0, 0, 0, 0",
 423                         #"setvl 0, 0, 8, 0, 1, 1",
 424                         "sv.lwz/els *12, 4(1)",
 425                         #"sv.lwz *12, 0(1)"
 426                         ])
 427         lst = list(lst)
 428
 429         # SVSTATE (in this case, VL=4)
 430         svstate = SVP64State()
 431         svstate.vl = 8 # VL
 432         svstate.maxvl = 8 # MAXVL
 433         print ("SVSTATE", bin(svstate.asint()))
 434
 435         regs = [0] * 64
 436
 437         avi = [0x001, 0x102, 0x203, 0x304, 0x405, 0x506, 0x607, 0x708]
 438         n = len(avi)
 439         levels = n.bit_length() - 1
 440         ri = list(range(n))
 441         ri = [ri[reverse_bits(i, levels)] for i in range(n)]
 442         av = halfrev2(avi, False)
 443         av = [av[ri[i]] for i in range(n)]
 444
 445         with Program(lst, bigendian=False) as program:
 446             sim = self.run_tst_program(program, svstate=svstate,
 447                                                 initial_regs=regs)
 448             mem = sim.mem.dump(printout=False)
 449             print ("Mem")
 450             print (mem)
 451
 452             self.assertEqual(mem, [(16, 0x010200000001),
 453                                    (24, 0x030400000203),
 454                                    (32, 0x050600000405),
 455                                    (40, 0x070800000607)])
 456             # from STs
 457             for i in range(len(avi)):
 458                 print ("st gpr", i, sim.gpr(i+4), hex(avi[i]))
 459             for i in range(len(avi)):
 460                 self.assertEqual(sim.gpr(i+4), avi[i])
 461             # combination of bit-reversed load with a DCT half-swap REMAP
 462             # schedule
 463             for i in range(len(avi)):
 464                 print ("ld gpr", i, sim.gpr(i+12), hex(av[i]))
 465             for i in range(len(avi)):
 466                 self.assertEqual(sim.gpr(i+12), av[i])
 467
 468     def test_sv_load_store_bitreverse_remap_halfswap_idct(self):
 469         """>>> lst = ["addi 1, 0, 0x0010",
 470                         "addi 2, 0, 0x0000",
 471                         "addi 4, 0, 0x101",
 472                         "addi 5, 0, 0x202",
 473                         "addi 6, 0, 0x303",
 474                         "addi 7, 0, 0x404",
 475                         "addi 8, 0, 0x505",
 476                         "addi 9, 0, 0x606",
 477                         "addi 10, 0, 0x707",
 478                         "addi 11, 0, 0x808",
 479                         "sv.stw *5, 0(1)",
 480                         "svshape 8, 1, 1, 6, 0",
 481                         "svremap 31, 1, 2, 3, 0, 0, 0",
 482                         "sv.lwz/els *12, 4(1)"]
 483
 484         bitreverse LD is computed as:
 485         for i in range(VL):
 486             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 487
 488         bitreversal of 0 1 2 3 in binary 0b00 0b01 0b10 0b11
 489         produces       0 2 1 3 in binary 0b00 0b10 0b01 0b11
 490
 491         and thus creates the butterfly needed for one iteration of FFT.
 492         the RC (shift) is to be able to offset the LDs by Radix-2 spans
 493
 494         on top of the bit-reversal is a REMAP for half-swaps for DCT
 495         in-place.
 496         """
 497         lst = SVP64Asm(["addi 1, 0, 0x0010",
 498                         "addi 2, 0, 0x0000",
 499                         "addi 4, 0, 0x001",
 500                         "addi 5, 0, 0x102",
 501                         "addi 6, 0, 0x203",
 502                         "addi 7, 0, 0x304",
 503                         "addi 8, 0, 0x405",
 504                         "addi 9, 0, 0x506",
 505                         "addi 10, 0, 0x607",
 506                         "addi 11, 0, 0x708",
 507                         "sv.stw *4, 0(1)",  # scalar r1 + 0 + wordlen*offs
 508                         "svshape 8, 1, 1, 14, 0",
 509                         "svremap 16, 0, 0, 0, 0, 0, 0",
 510                         #"setvl 0, 0, 8, 0, 1, 1",
 511                         "sv.lwz/els *12, 4(1)",
 512                         #"sv.lwz *12, 0(1)"
 513                         ])
 514         lst = list(lst)
 515
 516         # SVSTATE (in this case, VL=4)
 517         svstate = SVP64State()
 518         svstate.vl = 8 # VL
 519         svstate.maxvl = 8 # MAXVL
 520         print ("SVSTATE", bin(svstate.asint()))
 521
 522         regs = [0] * 64
 523
 524         avi = [0x001, 0x102, 0x203, 0x304, 0x405, 0x506, 0x607, 0x708]
 525         n = len(avi)
 526         levels = n.bit_length() - 1
 527         ri = list(range(n))
 528         ri = [ri[reverse_bits(i, levels)] for i in range(n)]
 529         av = [avi[ri[i]] for i in range(n)]
 530         av = halfrev2(av, True)
 531
 532         with Program(lst, bigendian=False) as program:
 533             sim = self.run_tst_program(program, svstate=svstate,
 534                                                 initial_regs=regs)
 535             mem = sim.mem.dump(printout=False)
 536             print ("Mem")
 537             print (mem)
 538
 539             self.assertEqual(mem, [(16, 0x010200000001),
 540                                    (24, 0x030400000203),
 541                                    (32, 0x050600000405),
 542                                    (40, 0x070800000607)])
 543             # from STs
 544             for i in range(len(avi)):
 545                 print ("st gpr", i, sim.gpr(i+4), hex(avi[i]))
 546             for i in range(len(avi)):
 547                 self.assertEqual(sim.gpr(i+4), avi[i])
 548             # combination of bit-reversed load with a DCT half-swap REMAP
 549             # schedule
 550             for i in range(len(avi)):
 551                 print ("ld gpr", i, sim.gpr(i+12), hex(av[i]))
 552             for i in range(len(avi)):
 553                 self.assertEqual(sim.gpr(i+12), av[i])
 554
 555     def run_tst_program(self, prog, initial_regs=None,
 556                               svstate=None, initial_fprs=None):
 557         if initial_regs is None:
 558             initial_regs = [0] * 32
 559         if initial_fprs is None:
 560             initial_fprs = [0] * 32
 561         simulator = run_tst(prog, initial_regs, svstate=svstate,
 562                                   initial_fprs=initial_fprs)
 563         print ("GPRs")
 564         simulator.gpr.dump()
 565         print ("FPRs")
 566         simulator.fpr.dump()
 567         return simulator
 568
 569
 570 if __name__ == "__main__":
 571     unittest.main()