src/openpower/decoder/isa/test_caller_svp64_ldst.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from openpower.decoder.helpers import fp64toselectable
  17 from openpower.decoder.isa.remap_dct_yield import (halfrev2, reverse_bits,
  18                                                   )
  19 from copy import deepcopy
  20
  21
  22 class DecoderTestCase(FHDLTestCase):
  23
  24     def _check_regs(self, sim, expected):
  25         for i in range(32):
  26             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  27
  28     def _check_fpregs(self, sim, expected):
  29         for i in range(32):
  30             self.assertEqual(sim.fpr(i), SelectableInt(expected[i], 64))
  31
  32     def test_sv_load_store_elementstride(self):
  33         """>>> lst = ["addi 1, 0, 0x0010",
  34                         "addi 2, 0, 0x0008",
  35                         "addi 4, 0, 0x1234",
  36                         "addi 5, 0, 0x1235",
  37                         "sv.stw/els 4.v, 16(1)",
  38                         "sv.lwz/els 8.v, 16(1)"]
  39
  40         note: element stride mode is only enabled when RA is a scalar
  41         and when the immediate is non-zero
  42
  43         element stride is computed as:
  44         for i in range(VL):
  45             EA = (RA|0) + EXTS(D) * i
  46         """
  47         lst = SVP64Asm(["addi 1, 0, 0x0010",
  48                         "addi 2, 0, 0x0008",
  49                         "addi 4, 0, 0x1234",
  50                         "addi 5, 0, 0x1235",
  51                         "sv.stw/els 4.v, 24(1)",  # scalar r1 + 16 + 24*offs
  52                         "sv.lwz/els 8.v, 24(1)"]) # scalar r1 + 16 + 24*offs
  53         lst = list(lst)
  54
  55         # SVSTATE (in this case, VL=2)
  56         svstate = SVP64State()
  57         svstate.vl = 2 # VL
  58         svstate.maxvl = 2 # MAXVL
  59         print ("SVSTATE", bin(svstate.asint()))
  60
  61         with Program(lst, bigendian=False) as program:
  62             sim = self.run_tst_program(program, svstate=svstate)
  63             mem = sim.mem.dump(printout=False)
  64             print (mem)
  65             # contents of memory expected at:
  66             #    element 0:   r1=0x10, D=24, => EA = 0x10+24*0 = 16 (0x10)
  67             #    element 1:   r1=0x10, D=24, => EA = 0x10+24*1 = 40 (0x28)
  68             # therefore, at address 0x10 ==> 0x1234
  69             # therefore, at address 0x28 ==> 0x1235
  70             expected_mem = [(16, 0x1234),
  71                             (40, 0x1235)]
  72             self.assertEqual(mem, expected_mem)
  73             print(sim.gpr(1))
  74             self.assertEqual(sim.gpr(8), SelectableInt(0x1234, 64))
  75             self.assertEqual(sim.gpr(9), SelectableInt(0x1235, 64))
  76
  77     def test_sv_load_store_unitstride(self):
  78         """>>> lst = ["addi 1, 0, 0x0010",
  79                         "addi 2, 0, 0x0008",
  80                         "addi 5, 0, 0x1234",
  81                         "addi 6, 0, 0x1235",
  82                         "sv.stw 8.v, 8(1)",
  83                         "sv.lwz 12.v, 8(1)"]
  84
  85         note: unit stride mode is only enabled when RA is a scalar.
  86
  87         unit stride is computed as:
  88         for i in range(VL):
  89             EA = (RA|0) + EXTS(D) + LDSTsize * i
  90         where for stw and lwz, LDSTsize is 4 because it is 32-bit words
  91         """
  92         lst = SVP64Asm(["addi 1, 0, 0x0010",
  93                         "addi 2, 0, 0x0008",
  94                         "addi 8, 0, 0x1234",
  95                         "addi 9, 0, 0x1235",
  96                         "sv.stw 8.v, 8(1)",  # scalar r1 + 8 + wordlen*offs
  97                         "sv.lwz 12.v, 8(1)"]) # scalar r1 + 8 + wordlen*offs
  98         lst = list(lst)
  99
 100         # SVSTATE (in this case, VL=2)
 101         svstate = SVP64State()
 102         svstate.vl = 2 # VL
 103         svstate.maxvl = 2 # MAXVL
 104         print ("SVSTATE", bin(svstate.asint()))
 105
 106         with Program(lst, bigendian=False) as program:
 107             sim = self.run_tst_program(program, svstate=svstate)
 108             mem = sim.mem.dump(printout=False)
 109             print ("Mem")
 110             print (mem)
 111             # contents of memory expected at:
 112             #    element 0:   r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*0 = 0x24
 113             #    element 1:   r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*8 = 0x28
 114             # therefore, at address 0x24 ==> 0x1234
 115             # therefore, at address 0x28 ==> 0x1235
 116             self.assertEqual(mem, [(24, 0x123500001234)])
 117             print(sim.gpr(1))
 118             self.assertEqual(sim.gpr(12), SelectableInt(0x1234, 64))
 119             self.assertEqual(sim.gpr(13), SelectableInt(0x1235, 64))
 120
 121     def test_sv_load_store_shifted(self):
 122         """>>> lst = ["addi 1, 0, 0x0010",
 123                         "addi 2, 0, 0x0004",
 124                         "addi 3, 0, 0x0002",
 125                         "addi 5, 0, 0x101",
 126                         "addi 6, 0, 0x202",
 127                         "addi 7, 0, 0x303",
 128                         "addi 8, 0, 0x404",
 129                         "sv.stw 5.v, 0(1)",
 130                         "sv.lwzsh 12.v, 4(1), 2"]
 131
 132         shifted LD is computed as:
 133         for i in range(VL):
 134             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 135         """
 136         lst = SVP64Asm(["addi 1, 0, 0x0010",
 137                         "addi 2, 0, 0x0000",
 138                         "addi 5, 0, 0x101",
 139                         "addi 6, 0, 0x202",
 140                         "addi 7, 0, 0x303",
 141                         "addi 8, 0, 0x404",
 142                         "sv.stw 5.v, 0(1)",  # scalar r1 + 0 + wordlen*offs
 143                         "sv.lwzsh 12.v, 4(1), 2"]) # bit-reversed
 144         lst = list(lst)
 145
 146         # SVSTATE (in this case, VL=4)
 147         svstate = SVP64State()
 148         svstate.vl = 4 # VL
 149         svstate.maxvl = 4 # MAXVL
 150         print ("SVSTATE", bin(svstate.asint()))
 151
 152         with Program(lst, bigendian=False) as program:
 153             sim = self.run_tst_program(program, svstate=svstate)
 154             mem = sim.mem.dump(printout=False)
 155             print (mem)
 156
 157             self.assertEqual(mem, [(16, 0x020200000101),
 158                                    (24, 0x040400000303)])
 159             print(sim.gpr(1))
 160             # from STs
 161             self.assertEqual(sim.gpr(5), SelectableInt(0x101, 64))
 162             self.assertEqual(sim.gpr(6), SelectableInt(0x202, 64))
 163             self.assertEqual(sim.gpr(7), SelectableInt(0x303, 64))
 164             self.assertEqual(sim.gpr(8), SelectableInt(0x404, 64))
 165             # r1=0x10, RC=0, offs=4: contents of memory expected at:
 166             #    element 0:   EA = r1 + 0b00*4 => 0x10 + 0b00*4 => 0x10
 167             #    element 1:   EA = r1 + 0b01*4 => 0x10 + 0b01*4 => 0x18
 168             #    element 2:   EA = r1 + 0b10*4 => 0x10 + 0b10*4 => 0x14
 169             #    element 3:   EA = r1 + 0b11*4 => 0x10 + 0b11*4 => 0x1c
 170             # therefore loaded from (bit-reversed indexing):
 171             #    r9  => mem[0x10] which was stored from r5
 172             #    r10 => mem[0x18] which was stored from r6
 173             #    r11 => mem[0x18] which was stored from r7
 174             #    r12 => mem[0x1c] which was stored from r8
 175             self.assertEqual(sim.gpr(12), SelectableInt(0x101, 64))
 176             self.assertEqual(sim.gpr(13), SelectableInt(0x202, 64))
 177             self.assertEqual(sim.gpr(14), SelectableInt(0x303, 64))
 178             self.assertEqual(sim.gpr(15), SelectableInt(0x404, 64))
 179
 180     def test_sv_load_store_shifted_fp(self):
 181         """>>> lst = ["addi 1, 0, 0x0010",
 182                         "addi 2, 0, 0x0004",
 183                         "addi 3, 0, 0x0002",
 184                         "addi 5, 0, 0x101",
 185                         "addi 6, 0, 0x202",
 186                         "addi 7, 0, 0x303",
 187                         "addi 8, 0, 0x404",
 188                         "sv.std 5.v, 0(1)",
 189                         "sv.lfdbr 12.v, 4(1), 2"]
 190
 191         shifted LD is computed as:
 192         for i in range(VL):
 193             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 194         """
 195         lst = SVP64Asm(["addi 1, 0, 0x0010",
 196                         "addi 2, 0, 0x0000",
 197                         "addi 5, 0, 0x101",
 198                         "addi 6, 0, 0x202",
 199                         "addi 7, 0, 0x303",
 200                         "addi 8, 0, 0x404",
 201                         "sv.std 5.v, 0(1)", # scalar r1 + 0 + wordlen*offs
 202                         "sv.lfdsh 12.v, 8(1), 2"]) # shifted
 203         lst = list(lst)
 204
 205         # SVSTATE (in this case, VL=4)
 206         svstate = SVP64State()
 207         svstate.vl = 4 # VL
 208         svstate.maxvl = 4 # MAXVL
 209         print ("SVSTATE", bin(svstate.asint()))
 210
 211         fprs = [0] * 32
 212
 213         with Program(lst, bigendian=False) as program:
 214             sim = self.run_tst_program(program, svstate=svstate,
 215                                                 initial_fprs=fprs)
 216             mem = sim.mem.dump(printout=False)
 217             print (mem)
 218
 219             self.assertEqual(mem, [(16, 0x101),
 220                                    (24, 0x202),
 221                                    (32, 0x303),
 222                                    (40, 0x404),
 223                                   ])
 224             print(sim.gpr(1))
 225             # from STs
 226             self.assertEqual(sim.gpr(5), SelectableInt(0x101, 64))
 227             self.assertEqual(sim.gpr(6), SelectableInt(0x202, 64))
 228             self.assertEqual(sim.gpr(7), SelectableInt(0x303, 64))
 229             self.assertEqual(sim.gpr(8), SelectableInt(0x404, 64))
 230             # r1=0x10, RC=0, offs=4: contents of memory expected at:
 231             #    element 0:   EA = r1 + bitrev(0b00)*4 => 0x10 + 0b00*4 => 0x10
 232             #    element 1:   EA = r1 + bitrev(0b01)*4 => 0x10 + 0b10*4 => 0x18
 233             #    element 2:   EA = r1 + bitrev(0b10)*4 => 0x10 + 0b01*4 => 0x14
 234             #    element 3:   EA = r1 + bitrev(0b11)*4 => 0x10 + 0b10*4 => 0x1c
 235             # therefore loaded from (bit-reversed indexing):
 236             #    r9  => mem[0x10] which was stored from r5
 237             #    r10 => mem[0x18] which was stored from r6
 238             #    r11 => mem[0x18] which was stored from r7
 239             #    r12 => mem[0x1c] which was stored from r8
 240             self.assertEqual(sim.fpr(12), SelectableInt(0x101, 64))
 241             self.assertEqual(sim.fpr(13), SelectableInt(0x202, 64))
 242             self.assertEqual(sim.fpr(14), SelectableInt(0x303, 64))
 243             self.assertEqual(sim.fpr(15), SelectableInt(0x404, 64))
 244
 245     def test_sv_load_store_shifted2(self):
 246         """>>> lst = ["addi 1, 0, 0x0010",
 247                         "addi 2, 0, 0x0004",
 248                         "addi 3, 0, 0x0002",
 249                         "sv.stfs 4.v, 0(1)",
 250                         "sv.lfssh 12.v, 4(1), 2"]
 251
 252         shifted LD is computed as:
 253         for i in range(VL):
 254             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 255
 256         """
 257         lst = SVP64Asm(["addi 1, 0, 0x0010",
 258                         "addi 2, 0, 0x0000",
 259                         "sv.stfs 4.v, 0(1)",  # scalar r1 + 0 + wordlen*offs
 260                         "sv.lfssh 12.v, 4(1), 2"]) # shifted (by zero, but hey)
 261         lst = list(lst)
 262
 263         # SVSTATE (in this case, VL=4)
 264         svstate = SVP64State()
 265         svstate.vl = 4 # VL
 266         svstate.maxvl = 4 # MAXVL
 267         print ("SVSTATE", bin(svstate.asint()))
 268
 269         fprs = [0] * 32
 270         scalar_a = 1.3
 271         scalar_b = -2.0
 272         fprs[4] = fp64toselectable(1.0)
 273         fprs[5] = fp64toselectable(2.0)
 274         fprs[6] = fp64toselectable(3.0)
 275         fprs[7] = fp64toselectable(4.0)
 276
 277         # expected results, remember that bit-reversed load has been done
 278         expected_fprs = deepcopy(fprs)
 279         expected_fprs[12] = fprs[4] # 0b00 -> 0b00
 280         expected_fprs[13] = fprs[5] # 0b10 -> 0b01
 281         expected_fprs[14] = fprs[6] # 0b01 -> 0b10
 282         expected_fprs[15] = fprs[7] # 0b11 -> 0b11
 283
 284         with Program(lst, bigendian=False) as program:
 285             sim = self.run_tst_program(program, svstate=svstate,
 286                                                 initial_fprs=fprs)
 287             mem = sim.mem.dump(printout=False)
 288             print ("mem dump")
 289             print (mem)
 290
 291             print ("FPRs")
 292             sim.fpr.dump()
 293
 294             #self.assertEqual(mem, [(16, 0x020200000101),
 295             #                       (24, 0x040400000303)])
 296             self._check_fpregs(sim, expected_fprs)
 297
 298     def test_sv_load_store_remap_matrix(self):
 299         """>>> lst = ["addi 1, 0, 0x0010",
 300                         "addi 2, 0, 0x0004",
 301                         "addi 3, 0, 0x0002",
 302                         "addi 5, 0, 0x101",
 303                         "addi 6, 0, 0x202",
 304                         "addi 7, 0, 0x303",
 305                         "addi 8, 0, 0x404",
 306                         "sv.stw 4.v, 0(1)",  # scalar r1 + 0 + wordlen*offs
 307                         "svshape 3, 3, 4, 0, 0",
 308                         "svremap 1, 1, 2, 0, 0, 0, 0, 1",
 309                         "sv.lwz 20.v, 0(1)",
 310                         ]
 311
 312         REMAPed a LD operation via a Matrix Multiply Schedule,
 313         which is set up as 3x4 result
 314         """
 315         lst = SVP64Asm(["addi 1, 0, 0x0010",
 316                         "addi 2, 0, 0x0000",
 317                         "addi 4, 0, 0x101",
 318                         "addi 5, 0, 0x202",
 319                         "addi 6, 0, 0x303",
 320                         "addi 7, 0, 0x404",
 321                         "addi 8, 0, 0x505",
 322                         "addi 9, 0, 0x606",
 323                         "addi 10, 0, 0x707",
 324                         "addi 11, 0, 0x808",
 325                         "addi 12, 0, 0x909",
 326                         "addi 13, 0, 0xa0a",
 327                         "addi 14, 0, 0xb0b",
 328                         "addi 15, 0, 0xc0c",
 329                         "addi 16, 0, 0xd0d",
 330                         "addi 17, 0, 0xe0e",
 331                         "addi 18, 0, 0xf0f",
 332                         "sv.stw 4.v, 0(1)",  # scalar r1 + 0 + wordlen*offs
 333                         "svshape 3, 3, 4, 0, 0",
 334                         "svremap 1, 1, 2, 0, 0, 0, 0, 1",
 335                         "sv.lwz 20.v, 0(1)",
 336                         #"sv.lwzsh 12.v, 4(1), 2", # bit-reversed
 337                         ])
 338         lst = list(lst)
 339
 340         # SVSTATE (in this case, VL=4)
 341         svstate = SVP64State()
 342         svstate.vl = 12 # VL
 343         svstate.maxvl = 12 # MAXVL
 344         print ("SVSTATE", bin(svstate.asint()))
 345
 346         regs = [0] * 64
 347
 348         with Program(lst, bigendian=False) as program:
 349             sim = self.run_tst_program(program, svstate=svstate,
 350                                                 initial_regs=regs)
 351             mem = sim.mem.dump(printout=False)
 352             print ("Mem")
 353             print (mem)
 354
 355             self.assertEqual(mem, [(16, 0x020200000101),
 356                                    (24, 0x040400000303),
 357                                    (32, 0x060600000505),
 358                                    (40, 0x080800000707),
 359                                    (48, 0x0a0a00000909),
 360                                    (56, 0x0c0c00000b0b)])
 361             print(sim.gpr(1))
 362             # from STs
 363             self.assertEqual(sim.gpr(4), SelectableInt(0x101, 64))
 364             self.assertEqual(sim.gpr(5), SelectableInt(0x202, 64))
 365             self.assertEqual(sim.gpr(6), SelectableInt(0x303, 64))
 366             self.assertEqual(sim.gpr(7), SelectableInt(0x404, 64))
 367             self.assertEqual(sim.gpr(8), SelectableInt(0x505, 64))
 368             self.assertEqual(sim.gpr(9), SelectableInt(0x606, 64))
 369             self.assertEqual(sim.gpr(10), SelectableInt(0x707, 64))
 370             self.assertEqual(sim.gpr(11), SelectableInt(0x808, 64))
 371             # combination of bit-reversed load with a Matrix REMAP
 372             # schedule
 373             for i in range(3):
 374                 self.assertEqual(sim.gpr(20+i), SelectableInt(0x101, 64))
 375                 self.assertEqual(sim.gpr(23+i), SelectableInt(0x505, 64))
 376                 self.assertEqual(sim.gpr(26+i), SelectableInt(0x909, 64))
 377                 self.assertEqual(sim.gpr(29+i), SelectableInt(0x202, 64))
 378
 379     def test_sv_load_store_bitreverse_remap_halfswap(self):
 380         """>>> lst = ["addi 1, 0, 0x0010",
 381                         "addi 2, 0, 0x0000",
 382                         "addi 4, 0, 0x101",
 383                         "addi 5, 0, 0x202",
 384                         "addi 6, 0, 0x303",
 385                         "addi 7, 0, 0x404",
 386                         "addi 8, 0, 0x505",
 387                         "addi 9, 0, 0x606",
 388                         "addi 10, 0, 0x707",
 389                         "addi 11, 0, 0x808",
 390                         "sv.stw 5.v, 0(1)",
 391                         "svshape 8, 1, 1, 6, 0",
 392                         "svremap 31, 1, 2, 3, 0, 0, 0, 0",
 393                         "sv.lwzsh 12.v, 4(1), 2"]
 394
 395         shifted LD is computed as:
 396         for i in range(VL):
 397             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 398
 399         bitreversal of 0 1 2 3 in binary 0b00 0b01 0b10 0b11
 400         produces       0 2 1 3 in binary 0b00 0b10 0b01 0b11
 401
 402         and thus creates the butterfly needed for one iteration of FFT.
 403         the RC (shift) is to be able to offset the LDs by Radix-2 spans
 404
 405         on top of the bit-reversal is a REMAP for half-swaps for DCT
 406         in-place.
 407         """
 408         lst = SVP64Asm(["addi 1, 0, 0x0010",
 409                         "addi 2, 0, 0x0000",
 410                         "addi 4, 0, 0x001",
 411                         "addi 5, 0, 0x102",
 412                         "addi 6, 0, 0x203",
 413                         "addi 7, 0, 0x304",
 414                         "addi 8, 0, 0x405",
 415                         "addi 9, 0, 0x506",
 416                         "addi 10, 0, 0x607",
 417                         "addi 11, 0, 0x708",
 418                         "sv.stw 4.v, 0(1)",  # scalar r1 + 0 + wordlen*offs
 419                         "svshape 8, 1, 1, 6, 0",
 420                         "svremap 1, 0, 0, 0, 0, 0, 0, 1",
 421                         #"setvl 0, 0, 8, 0, 1, 1",
 422                         "sv.lwzsh 12.v, 4(1), 2",  # bit-reversed
 423                         #"sv.lwz 12.v, 0(1)"
 424                         ])
 425         lst = list(lst)
 426
 427         # SVSTATE (in this case, VL=4)
 428         svstate = SVP64State()
 429         svstate.vl = 8 # VL
 430         svstate.maxvl = 8 # MAXVL
 431         print ("SVSTATE", bin(svstate.asint()))
 432
 433         regs = [0] * 64
 434
 435         avi = [0x001, 0x102, 0x203, 0x304, 0x405, 0x506, 0x607, 0x708]
 436         n = len(avi)
 437         levels = n.bit_length() - 1
 438         ri = list(range(n))
 439         ri = [ri[reverse_bits(i, levels)] for i in range(n)]
 440         av = halfrev2(avi, False)
 441         av = [av[ri[i]] for i in range(n)]
 442
 443         with Program(lst, bigendian=False) as program:
 444             sim = self.run_tst_program(program, svstate=svstate,
 445                                                 initial_regs=regs)
 446             mem = sim.mem.dump(printout=False)
 447             print ("Mem")
 448             print (mem)
 449
 450             self.assertEqual(mem, [(16, 0x010200000001),
 451                                    (24, 0x030400000203),
 452                                    (32, 0x050600000405),
 453                                    (40, 0x070800000607)])
 454             # from STs
 455             for i in range(len(avi)):
 456                 print ("st gpr", i, sim.gpr(i+4), hex(avi[i]))
 457             for i in range(len(avi)):
 458                 self.assertEqual(sim.gpr(i+4), avi[i])
 459             # combination of bit-reversed load with a DCT half-swap REMAP
 460             # schedule
 461             for i in range(len(avi)):
 462                 print ("ld gpr", i, sim.gpr(i+12), hex(av[i]))
 463             for i in range(len(avi)):
 464                 self.assertEqual(sim.gpr(i+12), av[i])
 465
 466     def test_sv_load_store_bitreverse_remap_halfswap_idct(self):
 467         """>>> lst = ["addi 1, 0, 0x0010",
 468                         "addi 2, 0, 0x0000",
 469                         "addi 4, 0, 0x101",
 470                         "addi 5, 0, 0x202",
 471                         "addi 6, 0, 0x303",
 472                         "addi 7, 0, 0x404",
 473                         "addi 8, 0, 0x505",
 474                         "addi 9, 0, 0x606",
 475                         "addi 10, 0, 0x707",
 476                         "addi 11, 0, 0x808",
 477                         "sv.stw 5.v, 0(1)",
 478                         "svshape 8, 1, 1, 6, 0",
 479                         "svremap 31, 1, 2, 3, 0, 0, 0, 0",
 480                         "sv.lwzsh 12.v, 4(1), 2"]
 481
 482         bitreverse LD is computed as:
 483         for i in range(VL):
 484             EA = (RA|0) + (EXTS(D) * LDSTsize * i) << RC
 485
 486         bitreversal of 0 1 2 3 in binary 0b00 0b01 0b10 0b11
 487         produces       0 2 1 3 in binary 0b00 0b10 0b01 0b11
 488
 489         and thus creates the butterfly needed for one iteration of FFT.
 490         the RC (shift) is to be able to offset the LDs by Radix-2 spans
 491
 492         on top of the bit-reversal is a REMAP for half-swaps for DCT
 493         in-place.
 494         """
 495         lst = SVP64Asm(["addi 1, 0, 0x0010",
 496                         "addi 2, 0, 0x0000",
 497                         "addi 4, 0, 0x001",
 498                         "addi 5, 0, 0x102",
 499                         "addi 6, 0, 0x203",
 500                         "addi 7, 0, 0x304",
 501                         "addi 8, 0, 0x405",
 502                         "addi 9, 0, 0x506",
 503                         "addi 10, 0, 0x607",
 504                         "addi 11, 0, 0x708",
 505                         "sv.stw 4.v, 0(1)",  # scalar r1 + 0 + wordlen*offs
 506                         "svshape 8, 1, 1, 14, 0",
 507                         "svremap 16, 0, 0, 0, 0, 0, 0, 1",
 508                         #"setvl 0, 0, 8, 0, 1, 1",
 509                         "sv.lwzsh 12.v, 4(1), 2",  # bit-reversed
 510                         #"sv.lwz 12.v, 0(1)"
 511                         ])
 512         lst = list(lst)
 513
 514         # SVSTATE (in this case, VL=4)
 515         svstate = SVP64State()
 516         svstate.vl = 8 # VL
 517         svstate.maxvl = 8 # MAXVL
 518         print ("SVSTATE", bin(svstate.asint()))
 519
 520         regs = [0] * 64
 521
 522         avi = [0x001, 0x102, 0x203, 0x304, 0x405, 0x506, 0x607, 0x708]
 523         n = len(avi)
 524         levels = n.bit_length() - 1
 525         ri = list(range(n))
 526         ri = [ri[reverse_bits(i, levels)] for i in range(n)]
 527         av = [avi[ri[i]] for i in range(n)]
 528         av = halfrev2(av, True)
 529
 530         with Program(lst, bigendian=False) as program:
 531             sim = self.run_tst_program(program, svstate=svstate,
 532                                                 initial_regs=regs)
 533             mem = sim.mem.dump(printout=False)
 534             print ("Mem")
 535             print (mem)
 536
 537             self.assertEqual(mem, [(16, 0x010200000001),
 538                                    (24, 0x030400000203),
 539                                    (32, 0x050600000405),
 540                                    (40, 0x070800000607)])
 541             # from STs
 542             for i in range(len(avi)):
 543                 print ("st gpr", i, sim.gpr(i+4), hex(avi[i]))
 544             for i in range(len(avi)):
 545                 self.assertEqual(sim.gpr(i+4), avi[i])
 546             # combination of bit-reversed load with a DCT half-swap REMAP
 547             # schedule
 548             for i in range(len(avi)):
 549                 print ("ld gpr", i, sim.gpr(i+12), hex(av[i]))
 550             for i in range(len(avi)):
 551                 self.assertEqual(sim.gpr(i+12), av[i])
 552
 553     def run_tst_program(self, prog, initial_regs=None,
 554                               svstate=None, initial_fprs=None):
 555         if initial_regs is None:
 556             initial_regs = [0] * 32
 557         if initial_fprs is None:
 558             initial_fprs = [0] * 32
 559         simulator = run_tst(prog, initial_regs, svstate=svstate,
 560                                   initial_fprs=initial_fprs)
 561         print ("GPRs")
 562         simulator.gpr.dump()
 563         print ("FPRs")
 564         simulator.fpr.dump()
 565         return simulator
 566
 567
 568 if __name__ == "__main__":
 569     unittest.main()