src/openpower/decoder/isa/test_caller_svp64_ldst.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18
  19 class DecoderTestCase(FHDLTestCase):
  20
  21     def _check_regs(self, sim, expected):
  22         for i in range(32):
  23             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  24
  25     def test_sv_load_store_unitstride(self):
  26         """>>> lst = ["addi 1, 0, 0x0010",
  27                         "addi 2, 0, 0x0008",
  28                         "addi 5, 0, 0x1234",
  29                         "addi 6, 0, 0x1235",
  30                         "sv.stw 5.v, 8(1)",
  31                         "sv.lwz 9.v, 8(1)"]
  32
  33         note: unit stride mode is only enabled when RA is a scalar.
  34
  35         unit stride is computed as:
  36         for i in range(VL):
  37             EA = (RA|0) + EXTS(D) + LDSTsize * i
  38         where for stw and lwz, LDSTsize is 4 because it is 32-bit words
  39         """
  40         lst = SVP64Asm(["addi 1, 0, 0x0010",
  41                         "addi 2, 0, 0x0008",
  42                         "addi 5, 0, 0x1234",
  43                         "addi 6, 0, 0x1235",
  44                         "sv.stw 5.v, 8(1)",  # scalar r1 + 8 + wordlen*offs
  45                         "sv.lwz 9.v, 8(1)"]) # scalar r1 + 8 + wordlen*offs
  46         lst = list(lst)
  47
  48         # SVSTATE (in this case, VL=2)
  49         svstate = SVP64State()
  50         svstate.vl[0:7] = 2 # VL
  51         svstate.maxvl[0:7] = 2 # MAXVL
  52         print ("SVSTATE", bin(svstate.spr.asint()))
  53
  54         with Program(lst, bigendian=False) as program:
  55             sim = self.run_tst_program(program, svstate=svstate)
  56             mem = sim.mem.dump(printout=False)
  57             print (mem)
  58             # contents of memory expected at:
  59             #    element 0:   r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*0 = 0x24
  60             #    element 1:   r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*8 = 0x28
  61             # therefore, at address 0x24 ==> 0x1234
  62             # therefore, at address 0x28 ==> 0x1235
  63             self.assertEqual(mem, [(24, 0x123500001234)])
  64             print(sim.gpr(1))
  65             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  66             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  67
  68     def run_tst_program(self, prog, initial_regs=None,
  69                               svstate=None):
  70         if initial_regs is None:
  71             initial_regs = [0] * 32
  72         simulator = run_tst(prog, initial_regs, svstate=svstate)
  73         simulator.gpr.dump()
  74         return simulator
  75
  76
  77 if __name__ == "__main__":
  78     unittest.main()