1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
19 class DecoderTestCase(FHDLTestCase
):
21 def _check_regs(self
, sim
, expected
):
23 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
25 def test_sv_load_store_unitstride(self
):
26 """>>> lst = ["addi 1, 0, 0x0010",
33 lst
= SVP64Asm(["addi 1, 0, 0x0010",
37 "sv.stw 5.v, 8(1)", # scalar r1 + 8 + wordlen*offs
38 "sv.lwz 9.v, 8(1)"]) # scalar r1 + 8 + wordlen*offs
41 # SVSTATE (in this case, VL=2)
42 svstate
= SVP64State()
43 svstate
.vl
[0:7] = 2 # VL
44 svstate
.maxvl
[0:7] = 2 # MAXVL
45 print ("SVSTATE", bin(svstate
.spr
.asint()))
47 with
Program(lst
, bigendian
=False) as program
:
48 sim
= self
.run_tst_program(program
, svstate
=svstate
)
49 mem
= sim
.mem
.dump(printout
=False)
51 self
.assertEqual(mem
, [(24, 0x123500001234)])
53 self
.assertEqual(sim
.gpr(9), SelectableInt(0x1234, 64))
54 self
.assertEqual(sim
.gpr(10), SelectableInt(0x1235, 64))
56 def run_tst_program(self
, prog
, initial_regs
=None,
58 if initial_regs
is None:
59 initial_regs
= [0] * 32
60 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
)
65 if __name__
== "__main__":