1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
19 class DecoderTestCase(FHDLTestCase
):
21 def _check_regs(self
, sim
, expected
):
23 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
25 def test_sv_add_scalar_reduce(self
):
26 """>>> lst = ['sv.add/mr 1, 5.v, 1'
28 note: there are 2 adds (VL=2) but *three values involved*
31 * 1 = 5 + 1 => 0x101 + 0x202 => 0x303
32 * 1 = 6 + 1 => 0x303 + 0x404 => 0x707
34 isa
= SVP64Asm(['sv.add/mr 1, 5.v, 1'
37 print ("listing", lst
)
39 # initial values in GPR regfile
40 initial_regs
= [0] * 32
41 initial_regs
[1] = 0x0101
42 initial_regs
[5] = 0x0202
43 initial_regs
[6] = 0x0404
44 # SVSTATE (in this case, VL=2)
45 svstate
= SVP64State()
47 svstate
.maxvl
= 2 # MAXVL
48 print ("SVSTATE", bin(svstate
.asint()))
49 # copy before running, then compute answers
50 expected_regs
= deepcopy(initial_regs
)
52 expected_regs
[1] = (initial_regs
[1] + initial_regs
[5] +
53 initial_regs
[6]) # 0x0707
55 with
Program(lst
, bigendian
=False) as program
:
56 sim
= self
.run_tst_program(program
, initial_regs
,
58 self
._check
_regs
(sim
, expected_regs
)
60 def test_sv_add_prefix_sum(self
):
61 """>>> lst = ['sv.add/mr 2.v, 2.v, 1.v'
63 adds performed - not in reverse
64 * 2 = 2 + 1 => 1 + 2 => 3
65 * 3 = 3 + 2 => 3 + 3 => 6
66 * 4 = 4 + 3 => 4 + 6 => 10
70 isa
= SVP64Asm(['sv.add/mr 2.v, 2.v, 1.v'
73 print ("listing", lst
)
75 # initial values in GPR regfile
76 initial_regs
= [0] * 32
81 # SVSTATE (in this case, VL=2)
82 svstate
= SVP64State()
84 svstate
.maxvl
= 3 # MAXVL
85 print ("SVSTATE", bin(svstate
.asint()))
86 # copy before running, then compute answers
87 expected_regs
= deepcopy(initial_regs
)
89 print ("%d += %d" % (2+i
, 1+i
))
90 expected_regs
[2+i
] += expected_regs
[1+i
]
92 print ("expected", i
, expected_regs
[i
])
94 with
Program(lst
, bigendian
=False) as program
:
95 sim
= self
.run_tst_program(program
, initial_regs
,
97 self
._check
_regs
(sim
, expected_regs
)
99 def test_sv_add_prefix_sum_reverse(self
):
100 """>>> lst = ['sv.add/mrr 2.v, 2.v, 1.v'
102 adds performed - *in reverse order*
103 * 4 = 4 + 3 => 1 + 2 => 3
104 * 3 = 3 + 2 => 3 + 2 => 5
105 * 2 = 2 + 1 => 3 + 4 => 7
107 isa
= SVP64Asm(['sv.add/mrr 2.v, 2.v, 1.v'
110 print ("listing", lst
)
112 # initial values in GPR regfile
113 initial_regs
= [0] * 32
114 initial_regs
[1] = 0x4
115 initial_regs
[2] = 0x3
116 initial_regs
[3] = 0x2
117 initial_regs
[4] = 0x1
118 # SVSTATE (in this case, VL=2)
119 svstate
= SVP64State()
121 svstate
.maxvl
= 3 # MAXVL
122 print ("SVSTATE", bin(svstate
.asint()))
123 # copy before running, then compute answers
124 expected_regs
= deepcopy(initial_regs
)
127 print ("%d += %d" % (2+j
, 1+j
))
128 expected_regs
[2+j
] += expected_regs
[1+j
]
130 print ("expected", i
, expected_regs
[i
])
132 with
Program(lst
, bigendian
=False) as program
:
133 sim
= self
.run_tst_program(program
, initial_regs
,
135 self
._check
_regs
(sim
, expected_regs
)
137 def test_fp_muls_reduce(self
):
138 """>>> lst = ["sv.fmuls/mr 1, 2.v, 1",
140 note that VL=3 but *four values are involved*
141 answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
143 * FPR 1 starts at 7.0
144 * FPR 1 multiplied by FPR 2, -9.8
145 * FPR 1 multiplied by FPR 3, -9.8
146 * FPR 1 multiplied by FPR 4, 2.0
148 isa
= SVP64Asm(["sv.fmuls/mr 1, 2.v, 1",
151 print ("listing", lst
)
154 fprs
[1] = 0x401C000000000000 # 7.0
155 fprs
[2] = 0xC02399999999999A # -9.8
156 fprs
[3] = 0xC02399999999999A # -9.8
157 fprs
[4] = 0x4000000000000000 # 2.0
159 # SVSTATE (in this case, VL=2)
160 svstate
= SVP64State()
162 svstate
.maxvl
= 3 # MAXVL
163 print ("SVSTATE", bin(svstate
.asint()))
165 with
Program(lst
, bigendian
=False) as program
:
166 sim
= self
.run_tst_program(program
, svstate
=svstate
,
168 # answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
169 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4095023d20000000, 64))
170 # these should not have been changed
171 self
.assertEqual(sim
.fpr(2), SelectableInt(0xC02399999999999A, 64))
172 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC02399999999999A, 64))
173 self
.assertEqual(sim
.fpr(4), SelectableInt(0x4000000000000000, 64))
175 def test_sv_fpmadds(self
):
176 """>>> lst = ["sv.fmadds/mr 6, 2.v, 4.v, 6"
178 this example uses f6 as a multiply-accumulate-sum mapreduce
180 lst
= SVP64Asm(["sv.fmadds/mr 6, 2.v, 4.v, 6"
185 fprs
[2] = 0x401C000000000000 # 7.0
186 fprs
[3] = 0xC02399999999999A # -9.8
187 fprs
[4] = 0x4000000000000000 # 2.0
188 fprs
[5] = 0xC040266660000000 # -32.3
189 fprs
[6] = 0x4000000000000000 # 2.0
191 # SVSTATE (in this case, VL=2)
192 svstate
= SVP64State()
194 svstate
.maxvl
= 2 # MAXVL
195 print ("SVSTATE", bin(svstate
.asint()))
197 with
Program(lst
, bigendian
=False) as program
:
198 sim
= self
.run_tst_program(program
, svstate
=svstate
,
200 self
.assertEqual(sim
.fpr(6), SelectableInt(0x4074c8a3c0000000, 64))
202 def run_tst_program(self
, prog
, initial_regs
=None, svstate
=None,
205 if initial_regs
is None:
206 initial_regs
= [0] * 32
207 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
208 initial_fprs
=initial_fprs
,
217 if __name__
== "__main__":