src/openpower/decoder/isa/test_caller_svp64_mapreduce.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18
  19 class DecoderTestCase(FHDLTestCase):
  20
  21     def _check_regs(self, sim, expected):
  22         for i in range(32):
  23             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  24
  25     def test_sv_add_scalar_reduce(self):
  26         """>>> lst = ['sv.add/mr 1, 5.v, 1'
  27                        ]
  28         adds:
  29             * 1 starts at 0x0101
  30             * 1 = 5 + 1  => 0x101 + 0x202 => 0x303
  31             * 1 = 6 + 1  => 0x303 + 0x404 => 0x707
  32         """
  33         isa = SVP64Asm(['sv.add/mr 1, 5.v, 1'
  34                        ])
  35         lst = list(isa)
  36         print ("listing", lst)
  37
  38         # initial values in GPR regfile
  39         initial_regs = [0] * 32
  40         initial_regs[1] = 0x0101
  41         initial_regs[5] = 0x0202
  42         initial_regs[6] = 0x0404
  43         # SVSTATE (in this case, VL=2)
  44         svstate = SVP64State()
  45         svstate.vl[0:7] = 2 # VL
  46         svstate.maxvl[0:7] = 2 # MAXVL
  47         print ("SVSTATE", bin(svstate.spr.asint()))
  48         # copy before running, then compute answers
  49         expected_regs = deepcopy(initial_regs)
  50         expected_regs[1] = (initial_regs[1] + initial_regs[5] +
  51                             initial_regs[6])  # 0x0707
  52
  53         with Program(lst, bigendian=False) as program:
  54             sim = self.run_tst_program(program, initial_regs, svstate)
  55             self._check_regs(sim, expected_regs)
  56
  57     def run_tst_program(self, prog, initial_regs=None,
  58                               svstate=None):
  59         if initial_regs is None:
  60             initial_regs = [0] * 32
  61         simulator = run_tst(prog, initial_regs, svstate=svstate)
  62         simulator.gpr.dump()
  63         return simulator
  64
  65
  66 if __name__ == "__main__":
  67     unittest.main()