src/openpower/decoder/isa/test_caller_svp64_mapreduce.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18
  19 class DecoderTestCase(FHDLTestCase):
  20
  21     def _check_regs(self, sim, expected):
  22         for i in range(32):
  23             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  24
  25     def test_sv_add_scalar_reduce(self):
  26         """>>> lst = ['sv.add/mr 1, 5.v, 1'
  27                        ]
  28         adds:
  29             * 1 starts at 0x0101
  30             * 1 = 5 + 1  => 0x101 + 0x202 => 0x303
  31             * 1 = 6 + 1  => 0x303 + 0x404 => 0x707
  32         """
  33         isa = SVP64Asm(['sv.add/mr 1, 5.v, 1'
  34                        ])
  35         lst = list(isa)
  36         print ("listing", lst)
  37
  38         # initial values in GPR regfile
  39         initial_regs = [0] * 32
  40         initial_regs[1] = 0x0101
  41         initial_regs[5] = 0x0202
  42         initial_regs[6] = 0x0404
  43         # SVSTATE (in this case, VL=2)
  44         svstate = SVP64State()
  45         svstate.vl[0:7] = 2 # VL
  46         svstate.maxvl[0:7] = 2 # MAXVL
  47         print ("SVSTATE", bin(svstate.spr.asint()))
  48         # copy before running, then compute answers
  49         expected_regs = deepcopy(initial_regs)
  50         # r1 = r1 + r5 + r6
  51         expected_regs[1] = (initial_regs[1] + initial_regs[5] +
  52                             initial_regs[6])  # 0x0707
  53
  54         with Program(lst, bigendian=False) as program:
  55             sim = self.run_tst_program(program, initial_regs,
  56                                                 svstate=svstate)
  57             self._check_regs(sim, expected_regs)
  58
  59     def test_fp_muls_reduce(self):
  60         """>>> lst = ["sv.fmuls/mr 1, 2.v, 1",
  61                      ]
  62         """
  63         isa = SVP64Asm(["sv.fmuls/mr 1, 2.v, 1",
  64                      ])
  65         lst = list(isa)
  66         print ("listing", lst)
  67
  68         fprs = [0] * 32
  69         fprs[1] = 0x401C000000000000  # 7.0
  70         fprs[2] = 0xC02399999999999A  # -9.8
  71         fprs[3] = 0xC02399999999999A  # -9.8
  72         fprs[4] = 0x4000000000000000  # 2.0
  73
  74         # SVSTATE (in this case, VL=2)
  75         svstate = SVP64State()
  76         svstate.vl[0:7] = 3 # VL
  77         svstate.maxvl[0:7] = 3 # MAXVL
  78         print ("SVSTATE", bin(svstate.spr.asint()))
  79
  80         with Program(lst, bigendian=False) as program:
  81             sim = self.run_tst_program(program, svstate=svstate,
  82                                                 initial_fprs=fprs)
  83             # answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
  84             self.assertEqual(sim.fpr(1), SelectableInt(0x4095023d60000000, 64))
  85             # these should not have been changed
  86             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
  87             self.assertEqual(sim.fpr(3), SelectableInt(0xC02399999999999A, 64))
  88             self.assertEqual(sim.fpr(4), SelectableInt(0x4000000000000000, 64))
  89
  90
  91     def run_tst_program(self, prog, initial_regs=None, svstate=None,
  92                               initial_mem=None,
  93                               initial_fprs=None):
  94         if initial_regs is None:
  95             initial_regs = [0] * 32
  96         simulator = run_tst(prog, initial_regs, mem=initial_mem,
  97                                   initial_fprs=initial_fprs,
  98                                   svstate=svstate)
  99         print ("GPRs")
 100         simulator.gpr.dump()
 101         print ("FPRs")
 102         simulator.fpr.dump()
 103         return simulator
 104
 105
 106 if __name__ == "__main__":
 107     unittest.main()