src/openpower/decoder/isa/test_caller_svp64_mapreduce.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.decoder.isa.caller import SVP64State
   6 from openpower.decoder.isa.test_caller import run_tst
   7 from openpower.decoder.selectable_int import SelectableInt
   8 from openpower.simulator.program import Program
   9 from openpower.insndb.asm import SVP64Asm
  10
  11
  12 class DecoderTestCase(FHDLTestCase):
  13
  14     def _check_regs(self, sim, expected):
  15         for i in range(32):
  16             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  17
  18     def test_sv_add_scalar_reduce(self):
  19         """>>> lst = ['sv.add/mr 1, *5, 1'
  20                        ]
  21         note: there are 2 adds (VL=2) but *three values involved*
  22         adds:
  23             * 1 starts at 0x0101
  24             * 1 = 5 + 1  => 0x101 + 0x202 => 0x303
  25             * 1 = 6 + 1  => 0x303 + 0x404 => 0x707
  26         """
  27         isa = SVP64Asm(['sv.add/mr 1, *5, 1'
  28                         ])
  29         lst = list(isa)
  30         print("listing", lst)
  31
  32         # initial values in GPR regfile
  33         initial_regs = [0] * 32
  34         initial_regs[1] = 0x0101
  35         initial_regs[5] = 0x0202
  36         initial_regs[6] = 0x0404
  37         # SVSTATE (in this case, VL=2)
  38         svstate = SVP64State()
  39         svstate.vl = 2  # VL
  40         svstate.maxvl = 2  # MAXVL
  41         print("SVSTATE", bin(svstate.asint()))
  42         # copy before running, then compute answers
  43         expected_regs = deepcopy(initial_regs)
  44         # r1 = r1 + r5 + r6
  45         expected_regs[1] = (initial_regs[1] + initial_regs[5] +
  46                             initial_regs[6])  # 0x0707
  47
  48         with Program(lst, bigendian=False) as program:
  49             sim = self.run_tst_program(program, initial_regs,
  50                                        svstate=svstate)
  51             self._check_regs(sim, expected_regs)
  52
  53     def test_sv_add_prefix_sum(self):
  54         """>>> lst = ['sv.add/mr *2, *2, *1'
  55                        ]
  56             adds performed - not in reverse
  57             * 2 = 2 + 1  => 1 + 2  =>  3
  58             * 3 = 3 + 2  => 3 + 3  =>  6
  59             * 4 = 4 + 3  => 4 + 6  =>  10
  60
  61             pascal's triangle!
  62         """
  63         isa = SVP64Asm(['sv.add/mr *2, *2, *1'
  64                         ])
  65         lst = list(isa)
  66         print("listing", lst)
  67
  68         # initial values in GPR regfile
  69         initial_regs = [0] * 32
  70         initial_regs[1] = 0x1
  71         initial_regs[2] = 0x2
  72         initial_regs[3] = 0x3
  73         initial_regs[4] = 0x4
  74         # SVSTATE (in this case, VL=2)
  75         svstate = SVP64State()
  76         svstate.vl = 3  # VL
  77         svstate.maxvl = 3  # MAXVL
  78         print("SVSTATE", bin(svstate.asint()))
  79         # copy before running, then compute answers
  80         expected_regs = deepcopy(initial_regs)
  81         for i in range(3):
  82             print("%d += %d" % (2+i, 1+i))
  83             expected_regs[2+i] += expected_regs[1+i]
  84         for i in range(5):
  85             print("expected", i, expected_regs[i])
  86
  87         with Program(lst, bigendian=False) as program:
  88             sim = self.run_tst_program(program, initial_regs,
  89                                        svstate=svstate)
  90             self._check_regs(sim, expected_regs)
  91
  92     def test_sv_add_prefix_sum_reverse(self):
  93         """>>> lst = ['sv.add/mrr *2, *2, *1'
  94                        ]
  95             adds performed - *in reverse order*
  96             * 4 = 4 + 3  => 1 + 2  =>  3
  97             * 3 = 3 + 2  => 3 + 2  =>  5
  98             * 2 = 2 + 1  => 3 + 4  =>  7
  99         """
 100         isa = SVP64Asm(['sv.add/mrr *2, *2, *1'
 101                         ])
 102         lst = list(isa)
 103         print("listing", lst)
 104
 105         # initial values in GPR regfile
 106         initial_regs = [0] * 32
 107         initial_regs[1] = 0x4
 108         initial_regs[2] = 0x3
 109         initial_regs[3] = 0x2
 110         initial_regs[4] = 0x1
 111         # SVSTATE (in this case, VL=2)
 112         svstate = SVP64State()
 113         svstate.vl = 3  # VL
 114         svstate.maxvl = 3  # MAXVL
 115         print("SVSTATE", bin(svstate.asint()))
 116         # copy before running, then compute answers
 117         expected_regs = deepcopy(initial_regs)
 118         for i in range(3):
 119             j = 2-i
 120             print("%d += %d" % (2+j, 1+j))
 121             expected_regs[2+j] += expected_regs[1+j]
 122         for i in range(5):
 123             print("expected", i, expected_regs[i])
 124
 125         with Program(lst, bigendian=False) as program:
 126             sim = self.run_tst_program(program, initial_regs,
 127                                        svstate=svstate)
 128             self._check_regs(sim, expected_regs)
 129
 130     def test_fp_muls_reduce(self):
 131         """>>> lst = ["sv.fmuls/mr 1, *2, 1",
 132                      ]
 133         note that VL=3 but *four values are involved*
 134         answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
 135
 136         * FPR 1 starts at 7.0
 137         * FPR 1 multiplied by FPR 2, -9.8
 138         * FPR 1 multiplied by FPR 3, -9.8
 139         * FPR 1 multiplied by FPR 4, 2.0
 140         """
 141         isa = SVP64Asm(["sv.fmuls/mr 1, *2, 1",
 142                         ])
 143         lst = list(isa)
 144         print("listing", lst)
 145
 146         fprs = [0] * 32
 147         fprs[1] = 0x401C000000000000  # 7.0
 148         fprs[2] = 0xC02399999999999A  # -9.8
 149         fprs[3] = 0xC02399999999999A  # -9.8
 150         fprs[4] = 0x4000000000000000  # 2.0
 151
 152         # SVSTATE (in this case, VL=2)
 153         svstate = SVP64State()
 154         svstate.vl = 3  # VL
 155         svstate.maxvl = 3  # MAXVL
 156         print("SVSTATE", bin(svstate.asint()))
 157
 158         with Program(lst, bigendian=False) as program:
 159             sim = self.run_tst_program(program, svstate=svstate,
 160                                        initial_fprs=fprs)
 161             # answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
 162             self.assertEqual(sim.fpr(1), SelectableInt(0x4095023d20000000, 64))
 163             # these should not have been changed
 164             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
 165             self.assertEqual(sim.fpr(3), SelectableInt(0xC02399999999999A, 64))
 166             self.assertEqual(sim.fpr(4), SelectableInt(0x4000000000000000, 64))
 167
 168     def test_sv_fpmadds(self):
 169         """>>> lst = ["sv.fmadds/mr 6, *2, *4, 6"
 170                         ]
 171                 this example uses f6 as a multiply-accumulate-sum mapreduce
 172         """
 173         lst = SVP64Asm(["sv.fmadds/mr 6, *2, *4, 6"
 174                         ])
 175         lst = list(lst)
 176
 177         fprs = [0] * 32
 178         fprs[2] = 0x401C000000000000  # 7.0
 179         fprs[3] = 0xC02399999999999A  # -9.8
 180         fprs[4] = 0x4000000000000000  # 2.0
 181         fprs[5] = 0xC040266660000000  # -32.3
 182         fprs[6] = 0x4000000000000000  # 2.0
 183
 184         # SVSTATE (in this case, VL=2)
 185         svstate = SVP64State()
 186         svstate.vl = 2  # VL
 187         svstate.maxvl = 2  # MAXVL
 188         print("SVSTATE", bin(svstate.asint()))
 189
 190         with Program(lst, bigendian=False) as program:
 191             sim = self.run_tst_program(program, svstate=svstate,
 192                                        initial_fprs=fprs)
 193             self.assertEqual(sim.fpr(6), SelectableInt(0x4074c8a3c0000000, 64))
 194
 195     def run_tst_program(self, prog, initial_regs=None, svstate=None,
 196                         initial_mem=None,
 197                         initial_fprs=None):
 198         if initial_regs is None:
 199             initial_regs = [0] * 32
 200         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 201                             initial_fprs=initial_fprs,
 202                             svstate=svstate)
 203         print("GPRs")
 204         simulator.gpr.dump()
 205         print("FPRs")
 206         simulator.fpr.dump()
 207         return simulator
 208
 209
 210 if __name__ == "__main__":
 211     unittest.main()